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full-speed usb (12-mbps) function cy7c64013c cy7c64113c cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-08001 rev. *b revised march 3, 2006 full-speed usb (12-mbps) function [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 2 of 51 table of contents 1.0 features .................................................................................................................. .....................6 2.0 functional overview ....................................... .......................................... ...................... .......7 3.0 pin configurations ........................................................................................................ ..........9 4.0 product summary tabl es ................................................... ................................................1 0 4.1 pin assignments .......................................................................................................... ............10 4.2 i/o register summary ...................................................................................................... .........10 4.3 instruction set summary ................................................................................................... ........12 5.0 programming model ......................................................................................................... .....13 5.1 14-bit program counter (pc) ............................................................................................... .....13 5.1.1 program memory organization .................... ......................................................................... ..........14 5.2 8-bit accumulator (a) ..................................................................................................... ...........15 5.3 8-bit temporary register (x) .............................................................................................. ......15 5.4 8-bit program stack pointe r (psp) ...................... .......................................... ......................... ..15 5.4.1 data memory organization ...................... .......................................................................... .............15 5.5 8-bit data stack pointer (dsp) ............................................................................................ .....16 5.6 address modes ............................................................................................................. ............16 5.6.1 data (immediate) ........................................................................................................ .....................16 5.6.2 direct .................................................................................................................. .............................16 5.6.3 indexed ................................................................................................................. ..........................16 6.0 clocking .................................................................................................................. ...................17 7.0 reset ....................................... .......................................... .................................... .......................17 7.1 power-on reset (por) ...................................................................................................... ......17 7.2 watchdog reset (wdr) ...................................................................................................... ......17 8.0 suspend mode ............ .......................................... ................................ ........................ .............18 9.0 general-purpose i/o (gpio) ports ....................................................................................19 9.1 gpio configuration port ................................................................................................... ........20 9.2 gpio interrupt enable ports ............................................................................................... ......21 10.0 dac port .............................. .......................................... ......................................... ..................21 10.1 dac isink registers ...................................................................................................... ..........22 10.2 dac port interrupts ...................................................................................................... ...........23 11.0 12-bit free-running ti mer ....................................... ................................ ......................... ..23 12.0 i 2 c and hapi configuration register ...........................................................................24 13.0 i 2 c-compatible controller ..............................................................................................25 14.0 hardware assisted parallel in terface (hapi) ........................................ ................27 15.0 processor status and contro l register ...... ........................................... ................28 16.0 interrupts ................ ............................... ................................ ................................ ................29 16.1 interrupt vectors ........................................................................................................ ..............30 16.2 interrupt latency ........................................................................................................ .............31 16.3 usb bus reset interrupt .................................................................................................. .......31 16.4 timer interrupt .......................................................................................................... ...............31 16.5 usb endpoint interrupts .................................................................................................. .......31 [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 3 of 51 table of contents 16.6 dac interrupt ............................................................................................................ ..............31 16.7 gpio/hapi interrupt ...................................................................................................... .........32 16.8 i 2 c interrupt ................................................................................................................... ..........32 17.0 usb overview ............................................................................................................. .............33 17.1 usb serial interface engine (sie) ........................................................................................ ..33 17.2 usb enumeration .......................................................................................................... .........33 17.3 usb upstream port status and control ..................................................................................33 18.0 usb serial interface engine operation ......................................................................34 18.1 usb device address ....................................................................................................... ........34 18.2 usb device endpoints ..................................................................................................... .......35 18.3 usb control endpoint mode register .....................................................................................35 18.4 usb non-control endpoint mode registers ...........................................................................36 18.5 usb endpoint counter registers ........................................................................................... .36 18.6 endpoint mode/count registers update and locking mechanism .........................................37 19.0 usb mode tables .......................................................................................................... .........39 20.0 register summary ......................................................................................................... .......43 21.0 sample schematic ......................................................................................................... ........44 22.0 absolute maximum ratings ...............................................................................................45 23.0 electrical characteristics fosc = 6 mhz; operating temperature = 0 to 70c, v cc = 4.0v to 5.25v ........................45 24.0 switching characteristics (fosc = 6.0 mhz) ...................................................................................... 46 25.0 ordering information ..................................................................................................... ...48 26.0 package diagrams . .......................................... ................................ .............................. .......49 [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 4 of 51 list of figures figure 6-1. clock oscillator on-chip circuit ................................................................................... .......17 figure 7-1. watchdog reset (wdr) ............................................................................................... .......18 figure 9-1. block diagram of a gpio pin ........................................................................................ ......19 figure 9-2. port 0 data ........................................................................................................ ..................19 figure 9-3. port 1 data ........................................................................................................ ..................19 figure 9-4. port 2 data ........................................................................................................ ..................19 figure 9-5. port 3 data ........................................................................................................ ..................20 figure 9-6. gpio configuration register ........................................................................................ .......20 figure 9-7. port 0 interrupt enable............................................................................................ .............21 figure 9-8. port 1 interrupt enable............................................................................................ .............21 figure 9-9. port 2 interrupt enable............................................................................................ .............21 figure 9-10. port 3 interrupt enable........................................................................................... ............21 figure 10-1. block diagram of a dac pin........................................................................................ ......22 figure 10-2. dac port data ..................................................................................................... ..............22 figure 10-3. dac sink register................................................................................................. ............22 figure 10-4. dac port interrupt enable ......................................................................................... ........23 figure 10-5. dac port interrupt polarity ....................................................................................... .........23 figure 11-1. timer lsb register ................................................................................................ ...........23 figure 11-2. timer msb register ................................................................................................ ..........24 figure 11-3. timer block diagram ............................................................................................... ..........24 figure 12-1. hapi/i2c configuration register ................................................................................... ....24 figure 13-1. i 2 c data register...............................................................................................................2 5 figure 13-2. i2c status and control register ................................................................................... .....25 figure 15-1. processor status and control register ............................................................................. 28 figure 16-1. global interrupt enable register .................................................................................. .....29 figure 16-2. usb endpoint interrupt enable register ...........................................................................2 9 figure 16-3. interrupt controller function diagram ............................................................................. ..30 figure 16-4. gpio interrupt structure.......................................................................................... ..........32 figure 17-1. usb status and control register ................................................................................... ...34 figure 18-1. usb device address registers ...................................................................................... ...34 figure 18-2. usb device endpoint zero mode registers......................................................................35 figure 18-3. usb non-control device endpoint mode registers..........................................................36 figure 18-4. usb endpoint counter registers .................................................................................... ..36 figure 18-5. token/data packet flow diagram .................................................................................... .38 figure 24-1. clock timing ...................................................................................................... ................47 figure 24-2. usb data signal timing ............................................................................................ ........47 figure 24-3. hapi read by external interface from usb microcontroller..............................................47 figure 24-4. hapi write by external device to usb microcontroller .....................................................48 [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 5 of 51 list of tables table 4-1. pin assignments .................................................................................................... ..............10 table 4-2. i/o register summary ............................................................................................... ..........10 table 4-3. instruction set summary ............................................................................................ ..........12 table 9-1. gpio port output control truth table and interrupt polarity ..............................................20 table 12-1. hapi port configuration ........................................................................................... ..........25 table 12-2. i 2 c port configuration ........................................................................................................25 table 13-1. i 2 c status and control register bit definitions ..................................................................26 table 14-1. port 2 pin and hapi configur ation bit definitions .............................................................27 table 16-1. interrupt vector assignments ...................................................................................... .......31 table 17-1. control bit definition for upstream port .......................................................................... ...34 table 18-1. memory allocation for endpoints .................................................................................. ....35 table 19-1. usb register mode encoding ........................................................................................ ...39 table 19-2. details of modes for differing traffic conditions (see table 19-1 for the decode legend) ........... 41 [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 6 of 51 1.0 features ? full-speed usb microcontroller ? 8-bit usb optimized microcontroller ? harvard architecture ? 6-mhz external clock source ? 12-mhz internal cpu clock ? 48-mhz internal clock ? internal memory ? 256 bytes of ram ? 8 kb of prom (cy7c64013c, cy7c64113c) ? integrated master/slave i 2 c-compatible controller (100 khz) enabled through general-purpose i/o (gpio) pins ? hardware assisted parallel interface (hapi) for data transfer to external devices ? i/o ports ? three gpio ports (port 0 to 2) capable of sinking 7 ma per pin (typical) ? an additional gpio port (port 3) capable of sinking 12 ma per pin (typical) for high current requirements: leds ? higher current drive achievable by connecting multiple gpio pins together to drive a common output ? each gpio port can be configured as inputs with internal pull-ups or open drain outputs or traditional cmos outputs ? a digital to analog conver sion (dac) port with programmable current si nk outputs is available on the cy7c64113c devices ? maskable interrupts on all i/o pins ? 12-bit free-running timer with one microsecond clock ticks ? watchdog timer (wdt) ? internal power-on reset (por) ? usb specification compliance ? conforms to usb specification, version 1.1 ? conforms to usb hid sp ecification, version 1.1 ? supports up to five user configured endpoints up to four 8-byte data endpoints up to two 32-byt e data endpoints ? integrated usb transceivers ? improved output drivers to reduce emi ? operating voltage from 4.0v to 5.5v dc ? operating temperature from 0 to 70 degrees celsius ? cy7c64013c available in 28-pin soic and 28-pin pdip packages ? cy7c64113c available in 48-pin ssop packages ? industry-standard programmer support [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 7 of 51 2.0 functional overview the cy7c64013c and cy7c64113c are 8-bit one time programmab le microcontrollers that are designed for full-speed usb applications. the instruction set has been optimized specifically for usb operations, although the microcontrollers can be used for a variety of non-usb embedded applications. gpio the cy7c64013c features 19 gpio pins to support usb a nd other applications. the i/o pi ns are grouped into three ports (p0[7:0], p1[2:0], p2[6:2], p3[2:0]) where each port can be configured as inputs wi th internal pull-ups, open drain outputs, or traditional cmos outputs. there are 16 gpio pi ns (ports 0 and 1) which are rated at 7 ma typical sink current. port 3 pins are rated at 12 ma typical sink curr ent, a current sufficient to drive leds. multiple gpio pins can be conn ected together to drive a single output for more drive current capacity. additionally, ea ch gpio can be used to generate a gpio interrupt to the microcon - troller. all of the gpio interrupts sh are the same ?gpio? interrupt vector. the cy7c64113c has 32 gpio pins (p0[7:0], p1[7:0], p2[7:0], p3[7:0]) dac the cy7c64113c has four programmable sink current i/o pins (dac ) pins (p4[7,2:0]). every dac pin includes an integrated 14- k ? pull-up resistor. when a ?1? is written to a dac i/o pin, the output current sink is disabled and the output pin is driven hig h by the internal pull-up resistor. when a ?0? is written to a dac i/o pin, the inte rnal pull-up resistor is disabled and the out put pin provides the programmed amount of sink current. a dac i/o pin can be used as an input with an internal pull-up by writing a ?1? to the pin. the sink current for each dac i/o pin can be individually progra mmed to one of 16 values using dedicated isink registers. dac bits p4[1:0] can be used as high-current outputs with a programm able sink current range of 3.2 to 16 ma (typical). dac bits p4[7,2] have a programmable current sink range of 0.2 to 1.0 ma (t ypical). multiple dac pins can be connected together to drive a single output that requires more sink current capacity. each i/o pin can be used to generate a dac interrupt to the microcon- troller. also, the interrupt polarity for each dac i/o pin is individually programmable. clock the microcontroller uses an external 6-mhz crystal and an intern al oscillator to provide a reference to an internal pll-based clock generator. this technology allows the customer applicati on to use an inexpensive 6-mhz fu ndamental crystal that reduces the clock-related noise emissions (emi). a pll clock generator pr ovides the 6-, 12-, and 48-mhz clock signals for distribution within the microcontroller. memory the cy7c64013c and cy7c64113c have 8 kb of prom. power on reset, watchdog and free running time these parts include power-on reset logic, a watchdog timer, and a 12-bit free-running timer. the power-on reset (por) logic detects when power is applied to the device, resets the logic to a known state, and begins execut ing instructions at prom addre ss 0x0000. the watchdog timer is used to ensure the microcontrolle r recovers after a period of inactivity. the firmware may become inactive for a variety of reasons, including errors in the code or a hardware failure such as waiting for an interrupt that nev er occurs. i2c and hapi interface the microcontroller can communicate with exter nal electronics through the gpio pins. an i 2 c-compatible interface accommo- dates a 100-khz serial link with an external device. there is also a hardware assisted parallel interface (hapi) which can be used to transfer data to an external device. timer the free-running 12-bit timer clocked at 1 mhz provides two in terrupt sources, 128-s and 1.024 -ms. the timer can be used to measure the duration of an event under firmware control by read ing the timer at the start of the event and afte r the event is complete. the difference between the two readings indicates the du ration of the event in microseconds. the upper four bits of the timer are latched into an internal register when the firmwar e reads the lower eight bits. a read from the upper four bits a ctually reads data from the internal register, instead of the timer. th is feature eliminates the need fo r firmware to try to compensate if the upper four bits increment immediately after the lower eight bits are read. interrupts the microcontroller supports 11 maskable interrupts in the vector ed interrupt controller. interrupt sources include the usb bus reset interrupt, the 128-s (bit 6) and 1.024-ms (bit 9) outputs from the free-running timer, five usb endpoints, the dac port, the gpio ports, and the i 2 c-compatible master mode interface. the timer bits cause an interrupt (if enabled) when the bit toggles from low ?0? to high ?1.? the usb endpoints interrupt after the u sb host has written data to the endpoint fifo or after the usb controller sends a packet to the usb host. the dac ports have an ad ditional level of masking that allows the user to select whi ch dac inputs can cause a dac interrupt. the gpio ports also have a level of masking to select which gpio inputs can cause a gpio interrupt. for additional flexibility, the input transition polarity that causes an interrupt is programmable for each pin of the dac port. input transition polarity can be programmed for each gp io port as part of the port co nfiguration. the interrupt polar ity can be rising edge (?0? to ?1?) or falling edge (?1? to ?0?). [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 8 of 51 logic block diagram interrupt controller prom 12-bit timer reset watchdog timer power-on sclk i 2 c gpio port 1 gpio port 0 p0[7:0] p1[2:0] p1[7:3] sdata 8-bit bus 6-mhz crystal ram usb sie usb transceiver d+[0] d?[0] upstream usb port p3[2:0] dac port dac[0] dac[2] high current outputs cy7c64113c only 256 byte 8 kb clock 6 mhz 12-mhz 8-bit cpu *i 2 c-compatible interface enabled by firmware through interface p3[7:3] additional outputs high current pll 12 mhz 48 mhz divider gpio/ port 2 p2[0,1,7] p2[3]; data_ready p2[4]; stb p2[5]; oe p2[6]; cs p2[2]; latch_empty hapi p2[1:0] or p1[1:0] cy7c64113c only port 3 gpio dac[7] [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 9 of 51 3.0 pin configurations 1 2 3 4 5 6 7 9 11 12 13 14 15 16 18 17 xtalin 10 8 19 20 31 30 29 33 32 35 34 37 36 39 38 41 40 43 42 45 44 46 48 47 21 22 23 24 25 27 26 28 v cc p1[1] p1[0] p1[2] p1[4] p1[6] p3[0] p3[2] v ref p1[3] p1[5] p1[7] p3[1] d+[0] d?[0] p3[3] gnd p3[5] p3[7] p2[1] p2[3] gnd p2[5] p2[7] dac[7] p0[7] p0[5] p0[3] p0[1] dac[1] xtalout gnd p3[4] nc p3[6] p2[0] p2[2] gnd p2[4] p2[6] dac[0] v pp p0[0] p0[2] p0[4] p0[6] dac[2] cy7c64113c 48-pin ssop cy7c64013c 1 2 3 4 5 6 7 9 11 12 13 14 xtalin 10 8 15 17 16 19 18 21 20 23 22 25 24 26 28 27 v cc p1[1] p1[0] p1[2] p3[0] p3[2] gnd p2[2] v ref gnd p3[1] d+[0] d?[0] p2[3] p2[5] p0[7] p0[5] p0[3] p0[1] p0[6] xtalout p2[4] p2[6] v pp p0[0] p0[2] p0[4] 28-pin soic cy7c64013c 28-pin pdip top view 1 2 3 4 5 6 7 9 11 12 13 14 xtalin 10 8 15 17 16 19 18 21 20 23 22 25 24 26 28 27 v cc p1[0] p1[2] p3[0] p3[2] p2[2] gnd p2[4] v ref p1[1] gnd p3[1] d+[0] d?[0] p2[3] p2[5] p0[7] p0[5] p0[3] p0[1] xtalout p2[6] v pp p0[0] p0[2] p0[4] p0[6] [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 10 of 51 4.0 product summary tables 4.1 pin assignments 4.2 i/o register summary i/o registers are accessed via the i/o read (iord) and i/o write (iowr, iowx) instruct ions. iord reads data from the selected port into the accu mulator. iowr performs the reverse; it writes data from the accumulator to the selected port. indexed i/o wri te (iowx) adds the contents of x to the address in the instruction to form the port address and writes data from the accumulator t o the specified port. specifying address 0 (e.g., iowx 0h) means th e i/o register is selected solely by the contents of x. all undefined registers are reserved. it is important not to write to reserved registers as this may cause an undefined operati on or increased current consumption during opera tion. when writing to registers with rese rved bits, the reserved bits must be writ ten with ?0.? table 4-1. pin assignments name i/o 28-pin soic 28-pin pdip 48-pin ssop description d+[0], d?[0] i/o 6, 7 7, 8 7, 8 upstream port, usb differential data. p0 i/o p0[7:0] 10, 14, 11, 15, 12, 16, 13, 17 p0[7:0] 11, 15, 12, 16, 13, 17, 14, 18 p0[7:0] 20, 26, 21, 27, 22, 28, 23, 29 gpio port 0 capable of sinking 7 ma (typical). p1 i/o p1[2:0] 25, 27, 26 p1[2:0] 26, 4, 27 p1[7:0] 6, 43, 5, 44, 4, 45, 47, 46 gpio port 1 capable of sinking 7 ma (typical). p2 i/o p2[6:2] 19, 9, 20, 8, 21 p2[6:2] 20, 10, 21, 9, 23 p2[7:0] 18, 32, 17, 33, 15, 35, 14, 36 gpio port 2 capable of sinking 7 ma (typical). hapi is also supported through p2[6:2]. p3 i/o p3[2:0] 23, 5, 24 p3[2:0] 24, 6, 25 p3[7:0] 13, 37, 12, 39, 10, 41, 7, 42 gpio port 3, capable of sinking 12 ma (typical). dac i/o dac[7,2:0] 19, 25, 24, 31 dac port with programmable current sink outputs. dac[1:0] offer a programmabl e range of 3.2 to 16 ma typical. dac[7,2] have a programmable sink current range of 0.2 to 1.0 ma typical. xtal in in 2 2 2 6-mhz crystal or external clock input. xtal out out 1 1 1 6-mhz crystal out. v pp in 18 19 30 programming voltage supply, tie to ground during normal operation. v cc in 28 28 48 voltage supply. gnd in 4, 22 5, 22 11, 16, 34, 40 ground. v ref in 3 3 3 external 3.3v supply voltage for the differential data output buffers and the d+ pull-up. nc 38 no connect. table 4-2. i/o register summary register name i/o address read/write function page port 0 data 0x00 r/w gpio port 0 data 19 port 1 data 0x01 r/w gpio port 1 data 19 port 2 data 0x02 r/w gpio port 2 data 19 port 3 data 0x03 r/w gpio port 3 data 20 port 0 interrupt enable 0x04 w interrupt enable for pins in port 0 21 port 1 interrupt enable 0x05 w interrupt enable for pins in port 1 21 port 2 interrupt enable 0x06 w interrupt enable for pins in port 2 21 port 3 interrupt enable 0x07 w interrupt enable for pins in port 3 21 [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 11 of 51 gpio configuration 0x08 r/w gpio port configurations 20 hapi and i 2 c configuration 0x09 r/w hapi width and i 2 c position configuration 24 usb device address a 0x10 r/w usb device address a 34 ep a0 counter register 0x11 r/w usb address a, endpoint 0 counter 35 ep a0 mode register 0x12 r/w usb addr ess a, endpoint 0 configuration 34 ep a1 counter register 0x13 r/w usb address a, endpoint 1 counter 35 ep a1 mode register 0x14 r/w usb addr ess a, endpoint 1 configuration 35 ep a2 counter register 0x15 r/w usb address a, endpoint 2 counter 35 ep a2 mode register 0x16 r/w usb addr ess a, endpoint 2 configuration 35 usb status & control 0x1f r/w usb upstream port traffic status and control 34 global interrupt enable 0x20 r/w global interrupt enable 29 endpoint interrupt enable 0x21 r/w usb endpoint interrupt enables 29 timer (lsb) 0x24 r lower 8 bits of free-running timer (1 mhz) 23 timer (msb) 0x25 r upper 4 bits of free-running timer 24 wdt clear 0x26 w watchdog timer clear 18 i 2 c control & status 0x28 r/w i 2 c status and control 25 i 2 c data 0x29 r/w i 2 c data 25 dac data 0x30 r/w dac data 22 dac interrupt enable 0x31 w interrupt enable for each dac pin 23 dac interrupt polarity 0x32 w interru pt polarity for each dac pin 23 dac isink 0x38-0x3f w input sink cu rrent control for each dac pin 22 reserved 0x40 reserved ep a3 counter register 0x41 r/w usb address a, endpoint 3 counter 35 ep a3 mode register 0x42 r/w usb addr ess a, endpoint 3 configuration 34 ep a4 counter register 0x43 r/w usb address a, endpoint 4 counter 35 ep a4 mode register 0x44 r/w usb addr ess a, endpoint 4 configuration 35 reserved 0x48 reserved reserved 0x49 reserved reserved 0x4a reserved reserved 0x4b reserved reserved 0x4c reserved reserved 0x4d reserved reserved 0x4e reserved reserved 0x4f reserved reserved 0x50 reserved reserved 0x51 reserved processor status & control 0xff r/w microprocessor status and control register 26 table 4-2. i/o register summary (continued) register name i/o address read/write function page [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 12 of 51 4.3 instruction set summary refer to the cyasm assembler user?s guide for more details. table 4-3. instruction set summary mnemonic operand opcode cycles mnemonic operand opcode cycles halt 00 7 nop 20 4 add a,expr data 01 4 inc a acc 21 4 add a,[expr] direct 02 6 inc x x 22 4 add a,[x+expr] index 03 7 inc [expr] direct 23 7 adc a,expr data 04 4 inc [x+expr] index 24 8 adc a,[expr] direct 05 6 dec a acc 25 4 adc a,[x+expr] index 06 7 dec x x 26 4 sub a,expr data 07 4 dec [expr] direct 27 7 sub a,[expr] direct 08 6 dec [x+expr] index 28 8 sub a,[x+expr] index 09 7 iord expr address 29 5 sbb a,expr data 0a 4 iowr expr address 2a 5 sbb a,[expr] direct 0b 6 pop a 2b 4 sbb a,[x+expr] index 0c 7 pop x 2c 4 or a,expr data 0d 4 push a 2d 5 or a,[expr] direct 0e 6 push x 2e 5 or a,[x+expr] index 0f 7 swap a,x 2f 5 and a,expr data 10 4 swap a,dsp 30 5 and a,[expr] direct 11 6 mov [expr],a direct 31 5 and a,[x+expr] index 12 7 mov [x+expr],a index 32 6 xor a,expr data 13 4 or [expr],a direct 33 7 xor a,[expr] direct 14 6 or [x+expr],a index 34 8 xor a,[x+expr] index 15 7 and [expr],a direct 35 7 cmp a,expr data 16 5 and [x+expr],a index 36 8 cmp a,[expr] direct 17 7 xor [expr],a direct 37 7 cmp a,[x+expr] index 18 8 xor [x+expr],a index 38 8 mov a,expr data 19 4 iowx [x+expr] index 39 6 mov a,[expr] direct 1a 5 cpl 3a 4 mov a,[x+expr] index 1b 6 asl 3b 4 mov x,expr data 1c 4 asr 3c 4 mov x,[expr] direct 1d 5 rlc 3d 4 reserved 1e rrc 3e 4 xpage 1f 4 ret 3f 8 mov a,x 40 4 di 70 4 mov x,a 41 4 ei 72 4 mov psp,a 60 4 reti 73 8 call addr 50 - 5f 10 jc addr c0-cf 5 jmp addr 80-8f 5 jnc addr d0-df 5 call addr 90-9f 10 jacc addr e0-ef 7 jz addr a0-af 5 index addr f0-ff 14 jnz addr b0-bf 5 [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 13 of 51 5.0 programming model 5.1 14-bit program counter (pc) the 14-bit program counter (pc) allows access to up to 8 kb of prom available with the cy7c64x13c architecture. the top 32 bytes of the rom in the 8 kb part are reserved for testing purpose s. the program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000h. ty pically, this is a jump instruction to a reset handler that i nitializes the application (see interrupt vectors on page 30). the lower eight bits of the program counter are incremented as instructions are loaded and executed. the upper six bits of the program counter are incremented by executing an xpage instruction. as a result, th e last instruction executed within a 256-byte ?page? of sequential code should be an xpage instruction. the assembler directive ?xpageon? causes the assembler to insert xpage instructions automatically. because instructions can be either one or two bytes long, the assembler may occasionally need to insert a nop followed by an xpage to execute correctly. the address of the next instruction to be executed, the carry flag, and the zero flag are saved as two bytes on the program sta ck during an interrupt acknowledge or a call instruction. the pr ogram counter, carry flag, and zero flag are restored from the program stack during a reti instruction. only the pr ogram counter is restored during a ret instruction. the program counter cannot be accessed directly by the firmw are. the program stack can be examined by reading sram from location 0x00 and up. [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 14 of 51 5.1.1 program memory organization after reset address 14-bit pc 0x0000 program execution begins here after a reset 0x0002 usb bus reset interrupt vector 0x0004 128-s timer interrupt vector 0x0006 1.024-ms timer interrupt vector 0x0008 usb address a endpoint 0 interrupt vector 0x000a usb address a endpoint 1 interrupt vector 0x000c usb address a endpoint 2 interrupt vector 0x000e usb address a endpoint 3 interrupt vector 0x0010 usb address a endpoint 4 interrupt vector 0x0012 reserved 0x0014 dac interrupt vector 0x0016 gpio interrupt vector 0x0018 i 2 c interrupt vector 0x001a program memory begins here 0x1fdf 8 kb (-32) prom ends here (cy7c64013c, cy7c64113c) [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 15 of 51 5.2 8-bit accumulator (a) the accumulator is the general-purpose register for the microcontroller. 5.3 8-bit temporary register (x) the ?x? register is available to the firmware for temporary st orage of intermediate results. the microcontroller can perform in dexed operations based on the value in x. refer to section 5.6.3 for additional information. 5.4 8-bit program stack pointer (psp) during a reset, the program stack pointer ( psp) is set to 0x00 and ?grows? upward from this address. the psp may be set by firmware, using the mov psp,a instruction. the psp supports interrupt service under hardware control and call, ret, and reti instructions under firmware control. the psp is not readable by the firmware. during an interrupt acknowledge, interrupts are disabled and th e 14-bit program counter, carry flag, and zero flag are written as two bytes of data memory. the first byte is stored in the me mory addressed by the psp, then the psp is incremented. the second byte is stored in memory addressed by the psp, and the psp is incremented again. the overall ef fect is to store the program counter and flags on the program ?stack? and increment the psp by two. the return from interrupt (reti) instruction decrements the psp, then restores the second byte from memory addressed by the psp. the psp is decremented aga in and the first byte is restored from memory addressed by the psp. after the program counter and flags have been restored from stack, the interrupts are enable d. the overall effect is to restore the program counter and f lags from the program stack, decrement the psp by two, and reenable interrupts. the call subroutine (call) instruction st ores the program counter and flags on the program stack and increments the psp by two. the return from subroutine (ret) instructio n restores the program coun ter but not the flags from the program stack and decre- ments the psp by two. 5.4.1 data memory organization the cy7c64x13c microcontrollers provide 256 bytes of data ram. normally, the sram is partitioned into four areas: program stack, user variables, data stack, and usb endpoint fifos. the following is one example of where the program stack, data stack, and user variables areas could be located. after reset address 8-bit dsp 8-bit psp 0x00 program stack growth (move dsp [1] ) 8-bit dsp user selected data stack growth user variables usb fifo space for five endpoints [2] 0xff notes: 1. refer to section 5.5 for a description of dsp. 2. endpoint sizes are fixed by the endpoint size bit (i/o register 0x1f, bit 7), see table 18-1 . [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 16 of 51 5.5 8-bit data stack pointer (dsp) the data stack pointer (dsp) supports push and pop instruct ions that use the data stack for temporary storage. a push instruction pre-decrements the dsp, then writes data to the memory location addressed by the dsp. a pop instruction reads data from the memory location addressed by the dsp, then post-increments the dsp. during a reset, the dsp is reset to 0x00. a push instruction when dsp equals 0x00 writes data at the top of the data ram (address 0xff). this writes data to the memory area reserv ed for usb endpoint fifos. ther efore, the dsp should be indexed at an appropriate memory location that does not compromise t he program stack, user-defined me mory (variables), or the usb endpoint fifos. for usb applications, the firmware should set the dsp to an appr opriate location to avoid a memory conflict with ram dedicated to usb fifos. the memory requirements for the usb endpoint s are described in section 18.2. example assembly instructions to do this with two device addresses (fifos begin at 0xd8) are shown below: mov a,20h ; move 20 hex into accumulator (must be d8h or less) swap a,dsp ; swap accumulator value into dsp register 5.6 address modes the cy7c64013c and cy7c64113c microcontrollers support th ree addressing modes for instructions that require data operands: data, direct, and indexed. 5.6.1 data (immediate) ?data? address mode refers to a data operand that is actually a constant encoded in the instructio n. as an example, consider th e instruction that loads a with the constant 0xd8: ? mov a,0d8h this instruction requires two bytes of code where the first byte identifies the ?mov a? instruction with a data operand as the second byte. the second byte of the instruction is the constant ?0xd8.? a constant may be referred to by name if a prior ?equ? statement assigns the constant value to the name. for example, the following code is equivalent to the example shown above: ? dspinit: equ 0d8h ? mov a,dspinit 5.6.2 direct ?direct? address mode is used when the data operand is a variab le stored in sram. in that case, the one byte address of the variable is encoded in the instruction. as an example, consider an instruction that loads a with the contents of memory address location 0x10: ? mov a,[10h] normally, variable names are assigned to variable addresses usin g ?equ? statements to improve the readability of the assembler source code. as an example, the following c ode is equivalent to the example shown above: ? buttons: equ 10h ? mov a,[buttons] 5.6.3 indexed ?indexed? address mode allows the firmware to manipulate arrays of data stored in sram. the address of the data operand is the sum of a constant encoded in the instru ction and the contents of the ?x? register. normally, the constant is the ?base? add ress of an array of data and the x register contains an index that indicates which element of the array is actually addressed: ?array: equ 10h ?mov x,3 ? mov a,[x+array] this would have the effect of loading a wit h the fourth element of the sram ?array? that begins at address 0x10. the fourth element would be at address 0x13. [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 17 of 51 6.0 clocking the xtalin and xtalout are the clock pins to the microcontroller. the user can connect an external oscillator or a crystal to these pins. when using an external crystal, keep pcb traces betw een the chip leads and crystal as short as possible (less than 2 cm). a 6-mhz fundamental frequency parallel resonant crystal can be connected to these pins to provide a reference frequency for the internal pll. the two internal 30-pf load caps appear in series to the external crystal and would be equivalent to a 15 -pf load. therefore, the crystal must have a required load capacitance of about 15?18 pf. a ceramic resonator does not allow the microcontroller to meet the timing specifications of full sp eed usb and therefore a ceramic resonator is not recommended with these parts. an external 6-mhz clock can be applied to the xtalin pin if the xtalout pin is left open. grounding the xtalout pin when driving xtalin with an oscillator does not work because the internal clock is effectively shorted to ground. 7.0 reset the cy7c64x13c supports two resets: power-on reset (por) an d a watchdog reset (wdr). each of these resets causes: ? all registers to be restored to their default states, ? the usb device address to be set to 0, ? all interrupts to be disabled, ? the psp and data stack pointer (dsp) to be set to memory address 0x00. the occurrence of a reset is recorded in the processor status and control register, as described in section 15.0. bits 4 and 6 are used to record the occurrence of por and wdr, respectively. firmware can interrogate these bits to determine the cause of a reset. program execution starts at rom address 0x0000 after a reset. alth ough this looks like interrupt vector 0, there is an importan t difference. reset processing does not push t he program counter, carry flag, and zero flag onto program stack. the firmware reset handler should configure the hardware before the ?main? loop of co de. attempting to execute a ret or reti in the firmware reset handler causes unpredictable execution results. 7.1 power-on reset (por) when v cc is first applied to the chip, the power-on reset (por) si gnal is asserted and the cy7c64x13c enters a ?semi-suspend? state. during the semi-suspend stat e, which is different from the suspend state de fined in the usb specification, the oscillato r and all other blocks of the part are functional, except for t he cpu. this semi-suspend time ensures that both a valid v cc level is reached and that the internal pll has time to stabilize before full operation begins. when the v cc has risen above approximately 2.5v, and the oscillator is stable, the por is deasserted and t he on-chip timer starts counting. the first 1 ms of suspend time is not interruptible, and the semi-suspend state continues for an addi tional 95 ms unless the count is bypassed by a usb bus reset on the upstream port. the 95 ms provides time for v cc to stabilize at a valid operating voltage before the chip executes code. if a usb bus reset occurs on the upstream port during the 95-ms semi-suspend time, the se mi-suspend state is aborted and program execution begins immediately from address 0x0000. in this case, the bus reset interrupt is pending but not serviced until firmware sets the usb bus reset interrupt enable bit (bit 0 of register 0x20) and enables interrupts with the ei command. the por signal is asserted whenever v cc drops below approximately 2.5v, and remains asserted until v cc rises above this level again. behavior is the same as described above. 7.2 watchdog reset (wdr) the watchdog timer reset (wdr) occurs when the internal wa tchdog timer rolls over. writing any value to the write-only watchdog restart register at address 0x26 clears the timer. the ti mer rolls over and wdr occurs if it is not cleared within t watch (8 ms minimum) of the last clear. bit 6 of the processor status a nd control register is set to re cord this event (the register contents are set to 010x0001 by the wdr). a watchdog timer reset lasts for 2 ms, after which the micr ocontroller begins execution at rom address 0x0000. xtalout xtalin to internal pll 30 pf 30 pf (pin 1) (pin 2) figure 6-1. clock osci llator on-chip circuit [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 18 of 51 the usb transmitter is disabled by a watchdog reset because th e usb device address register is cleared (see section 18.1). otherwise, the usb controller would respond to all address 0 transactions. it is possible for the wdr bit of the processor status and control register (0xff) to be set following a por event. the wdr bit should be ignored if the firmware interro gates the processor status and control regi ster for a set condition on the wdr bit and if the por (bit 3 of register 0xff) bit is set. 8.0 suspend mode the cy7c64x13c can be placed into a low-power state by settin g the suspend bit of the processo r status and control register. all logic blocks in the devi ce are turned off except the gpio interrupt logic and the usb rece iver. the clock o scillator and pl l, as well as the free-running and watchdog timers, are shut down. only the occurrence of an enabled gpio interrupt or non-idle bus activity at a usb upstream or downstream port wakes the pa rt out of suspend. the run bit in the processor status and control register must be set to resume a part out of suspend. the clock oscillator restarts immediately after exiting suspen d mode. the microcontroller returns to a fully functional state 1 ms after the oscillator is stable. the microcontroller executes the instruction following the i/o write that placed the device int o suspend mode before servicing any interrupt requests. the gpio interrupt allows the controller to wake-up periodica lly and poll system components while maintaining a very low averag e power consumption. to achieve the lowest possible current during suspend mode, all i/o should be held at v cc or gnd. this also applies to internal port pins that may not be bonded in a particular package. typical code for entering suspend is shown below: ... ; all gpio set to low-power state (no floating pins) ... ; enable gpio interrupts if desired for wake-up mov a, 09h ; set suspend and run bits iowr ffh ; write to status and cont rol register - enter suspend, wait for usb activity (or gpio interrupt) nop ; this executes before any isr ... ; remaining code for exiting suspend routine last write to watchdog timer register no write to wdt register, so wdr goes high execution begins at reset vector 0x0000 t watch 2 ms figure 7-1. watchdog reset (wdr) [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 19 of 51 9.0 general-purpose i/o (gpio) ports there are up to 32 gpio pins (p0[7:0], p1 [7:0], p2[7:0], and p3[7:0]) for the hardw are interface. the number of gpio pins changes based on the package type of the chip. each port can be configured as inputs with inte rnal pull-ups, open drain outputs , or traditional cmos outputs. port 3 offers a higher current dr ive, with typical current sink capability of 12 ma. the data for each gpio port is accessible through the data registers. port data registers are shown in figure 9-2 through figure 9-5 , and are set to 1 on reset. port 0 data address 0x00 port 1 data address 0x01 port 2 data address 0x02 figure 9-1. block diagram of a gpio pin bit # 76543210 bit name p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset 11111111 figure 9-2. port 0 data bit # 76543210 bit name p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset 11111111 figure 9-3. port 1 data bit # 76543210 bit name p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset 11111111 figure 9-4. port 2 data gpio v cc 14 k ? gpio cfg mode 2-bits data out latch internal data bus port read port write interrupt enable control control interrupt controller q1 q3* q2 *port 0,1,2: low i sink port 3: high i sink data interrupt latch oe reg_bit strb data in latch (latch is transparent except in hapi mode) pin [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 20 of 51 port 3 data address 0x03 special care should be taken with any unused gpio data bits. an unus ed gpio data bit, either a pin on the chip or a port bit th at is not bonded on a particular package, must not be left floating when the device enters the suspend state. if a gpio data bit i s left floating, the leakage current caused by the floating bit may violate the suspend current limitation specified by the usb specifications. if a ?1? is written to the unused data bit and the port is configured with open dr ain outputs, the unused data bit remains in an indeterminate state. therefore, if an unused port bit is programmed in open-drain mode, it must be written with a ?0.? notice that the cy7c64013c part always requires that the data bits p1[7:3], p2[7,1,0], and p3[7:3] be written with a ?0.? in normal non-hapi mode, reads from a gpio port always return the present state of th e voltage at the pin, independent of the settings in the port data registers. if hapi mode is activated for a port, reads of that port return latched data as controlled by the hapi signals (see section 14.0). during rese t, all of the gpio pins are set to a hi gh-impedance input state (?1? in open drain mode). writing a ?0? to a gpio pin drives the pin low. in this state, a ?0? is always read on that gpio pin unless an external source overdrives the internal pull-down device. 9.1 gpio configuration port every gpio port can be programmed as input s with internal pull-ups, outputs low or hi gh, or hi-z (floating, the pin is not driv en internally). in addition, the interrupt polarity for ea ch port can be programmed. the port configuration bits ( figure 9-6 ) and the interrupt enable bit ( figure 9-7 through figure 9-10 ) determine the interrupt polarity of the port pins. gpio configuration address 0x08 as shown in table 9-1 below, a positive polarity on an input pin represents a rising edge interrupt (low to high), and a negative polarity on an input pin represents a falling edge interrupt (high to low). the gpio interrupt is generated when all of the following conditions are met: the interrupt enable bit of the associated port interrupt enable register is enabled, the gpio interrupt enable bit of the global interrupt enable register ( figure 16-1 ) is enabled, the interrupt e nable sense (bit 2, figure 15-1 ) is set, and the gpio pin of the port sees an event matching the interrupt polarity. the driving state of each gpio pin is determined by the value written to the pin?s data register ( figure 9-2 through figure 9-5 ) and by its associated port configuration bits as shown in the gpio configuration register ( figure 9-6 ). these ports are configured on a per-port basis, so all pins in a given port are configur ed together. the possible port configurations are detailed in table 9-1 . as shown in this table below, when a gpio port is configured with cmos outputs, interrupt s from that port are disabled. during reset, all of the bits in the gpio configuration register are written with ?0 ? to select hi-z mode for all gpio ports as the default configuration. bit # 76543210 bit name p3.7 p3.6 p3.5 p3.4 p3.3 p32 p3.1 p3.0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset 11111111 figure 9-5. port 3 data bit # 76543210 bit name port 3 config bit 1 port 3 config bit 0 port 2 config bit 1 port 2 config bit 0 port 1 config bit 1 port 1 config bit 0 port 0 config bit 1 port 0 config bit 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 figure 9-6. gpio configuration register table 9-1. gpio port output control truth table and interrupt polarity port config bit 1 port config bit 0 data register output drive strength interrupt enable bit interrupt polarity 1 1 0 output low 0 disabled 1 resistive 1 ? (falling edge) 1 0 0 output low 0 disabled 1 output high 1 disabled 0 1 0 output low 0 disabled 1 hi-z 1 ? (falling edge) 0 0 0 output low 0 disabled 1 hi-z 1 + (rising edge) [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 21 of 51 q1, q2, and q3 discussed below are the transistors referenced in figure 9-1 . the available gpio drive strength are: ? output low mode: the pin?s data register is set to ?0? writing ?0? to the pin?s data register puts the pin in output low mode, regardless of the conten ts of the port configuration bits[1:0]. in this mode, q1 and q2 are off. q3 is on. the gpio pin is driven low through q3. ? output high mode: the pin?s data register is set to 1 and the port configuration bits[1:0] is set to ?10? in this mode, q1 and q3 are off. q2 is on. the gpio is pulled up through q2. the gpio pin is capable of sourcing... of current. ? resistive mode: the pin?s data register is set to 1 and the port configuration bits[1:0] is set to ?11? q2 and q3 are off. q1 is on. the gpio pin is pulled up with an internal 14k ? resistor. in resistive mode, the pin may serve as an input. reading the pin?s data register returns a logic h igh if the pin is not driven low by an external source. ? hi-z mode : the pin?s data register is set to1 and port configuration bits[1:0] is set either ?00? or ?01? q1, q2, and q3 are all off. the gpio pin is not driven internal ly. in this mode, the pin may serve as an input. reading the port data register returns the actual logic value on the port pins. 9.2 gpio interrupt enable ports each gpio pin can be individually enabled or disabled as an inte rrupt source. the port 0?3 interrupt enable registers provide this feature with an interrupt enable bit for each gpio pin. when hapi mode (discussed in section 14.0) is enabled the gpio interrupts are blocked, including ports not used by h api, so gpio pins cannot be used as interrupt sources. during a reset, gpio interrupts are disabled by clearing all of th e gpio interrupt enable ports. writing a ?1? to a gpio interr upt enable bit enables gpio interrupts from the corresponding i nput pin. all gpio pins share a common interrupt, as discussed in section 16.7 port 0 interrupt enable address 0x04 port 2 interrupt enable address 0x06 port 3 interrupt enable address 0x07 10.0 dac port the cy7c64113c features a programmable current sink 4 bit port which is also known as a dac port. each of these port i/o pins have a programmable current sink. writing a ?1? to a dac i/o pin disables the output current si nk (isink dac) and drives t he i/o pin high through an integrated 14-k ? resistor. when a ?0? is written to a dac i/o pin, the isink dac is enabled and the pull- up resistor is disabl ed. this causes the i sink dac to sink current to drive the output low. figure 10-1 shows a block diagram of the dac port pin. bit # 76543210 bit name p0.7 intr enable p0.6 intr enable p0.5 intr enable p0.4 intr enable p0.3 intr enable p0.2 intr enable p0.1 intr enable p0.0 intr enabl e read/write wwwwwwww reset 00000000 figure 9-7. port 0 interrupt enable bit # 76543210 bit name p1.7 intr enable p1.6 intr enable p1.5 intr enable p1.4 intr enable p1.3 intr enabl p1.2 intr enable p1.1 intr enable p1.0 intr enable read/write wwwwwwww reset 00000000 figure 9-8. port 1 interrupt enable bit # 76543210 bit name p2.7 intr enable p2.6 intr enable p2.5 intr enable p2.4 intr enable p2.3 intr enable p2.2 intr enable p2.1 intr enable p2.0 intr enabl e read/write wwwwwwww reset 00000000 figure 9-9. port 2 interrupt enable bit # 76543210 bit name reserved (set to 0) p3.6 intr enable p3.5 intr enable p3.4 intr enable p3.3 intr enable p3.2 intr enable p3.1 intr enable p3.0 intr enable read/write wwwwwwww reset 00000000 figure 9-10. port 3 interrupt enable [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 22 of 51 the amount of sink current for the dac i/o pin is programmable ov er 16 values based on the co ntents of the dac isink register for that output pin. dac[1:0] are high-current outputs that are programmable from 3.2 ma to 16 ma (typic al). dac[7:2] are low- current outputs, programmable from 0.2 ma to 1.0 ma (typical). when the suspend bit in processor status and control register (see figure 15-1 ) is set, the isink dac bl ock of the dac circuitry is disabled. special care should be taken when the cy7c64x 13c device is placed in the suspend mode. the dac port data register (see figure 10-2 ) should normally be loaded with all ?1?s (0xff) befo re setting the suspend bit. if any of the dac bits are set to ?0? when the device is suspended, that dac input will float. the floating pin could result in excessive current cons umption by the device, unless an external load places the pin in a deterministic state. dac port data address 0x30 bit [1..0]: high cu rrent output 3.2 ma to 16 ma typical 1= i/o pin is an output pulled hgh through the 14-k ? resistor. 0 = i/o pin is an input with an internal 14-k ? pull-up resistor bit [3..2]: low curre nt output 0.2 ma to 1 ma typical 1= i/o pin is an output pulled hgh through the 14-k ? resistor. 0 = i/o pin is an input with an internal 14-k ? pull-up resistor 10.1 dac isink registers each dac i/o pin has an associated dac isink register to progra m the output sink current when t he output is driven low. the first isink register (0x38) controls the cu rrent for dac[0], the second (0x39) for dac[1], and so on until the isink register a t 0x3f controls the current to dac[7]. dac sink register address 0x38 -0x3f figure 10-1. block diagram of a dac pin bit # 76543210 bit name dac[7] reserved reserved reserv ed reserved dac[2] dac[1] dac[0] read/write r/w r/w r/w r/w r/w r/w r/w r/w reset 11111111 figure 10-2. dac port data bit # 76543210 bit name reserved reserved reserved reserved isink[3] isink[2] isink[1] isink[0] read/write wwww reset ----0000 figure 10-3. dac sink register v cc 14 k ? data out latch internal data bus dac read dac write interrupt enable interrupt logic to interrupt controller q1 internal buffer interrupt polarity isink dac isink register 4 bits dac i/o pin suspend (bit 3 of register 0xff) [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 23 of 51 bit [4..0]: isin k [x] (x= 0..4) writing all ?0?s to the isink register caus es 1/5 of the max current to flow through the dac i/o pin. writing all ?1?s to the isink register provides the maximum current flow through the pin. the other 14 st ates of the dac sink current are evenly spaced between these two values. bit [7..5]: reserved 10.2 dac port interrupts a dac port interrupt can be enabled/disabled for each pin individua lly. the dac port interrupt e nable register provides this feature with an interrupt enable bit for each dac i/o pin.all of the dac port interrupt enable regi ster bits are cleared to ?0? during a reset. all dac pins share a common in terrupt, as explained in section 16.6. dac port interrupt address 0x31 bit [7..0]: enable bit x (x= 0..2, 7) 1= enables interrupts from the corresponding bit position; 0= disables interrupts from the corresponding bit position as an additional benefit, the interrupt polarity for each dac pin is programmable with the dac port interrupt polarity register . writing a ?0? to a bit selects negative polarity (falling edge) that causes an interrupt (if enabled) if a falling edge transit ion occurs on the corresponding input pin. writing a ?1? to a bit in this register selects positive polarity (rising edge) that causes an interrupt (if enabled) if a rising edge transition occurs on the corresponding input pin. all of the dac port interrupt polarity register bits are cleared during a reset. dac port interrupt polarity address 0x32 bit [7..0]: enable bit x (x= 0..2, 7) 1= selects positive polarity (rising edge) that causes an interrupt (if enabled); 0= selects negative polarity (falling edge) that causes an interrupt (if enabled) 11.0 12-bit free-running timer the 12-bit timer provides two interrupts (128-s and 1.024-ms) and allows the firmware to directly time events that are up to 4 ms in duration. the lower 8 bits of the timer can be read dire ctly by the firmware. reading the lower 8 bits latches the upper 4 bits into a temporary register. when the firmware reads the upper 4 bits of the timer, it is accessing the count stored in the temporary register. the effect of this logic is to ensure a st able 12-bit timer value can be read, even when the two reads are separated in time. timer lsb address 0x24 bit [7:0]: timer lower 8 bits bit # 76543210 bit name enable bit 7 reserved reserved reserved reserved enable bit 2 enable bit 1 enable bit 0 read/write wwwwwwww reset 00000000 figure 10-4. dac port interrupt enable bit # 76543210 bit name enable bit 7 reserved reserved reserved reserved enable bit 2 enable bit 1 enable bit 0 read/write wwwwwwww reset 00000000 figure 10-5. dac port interrupt polarity bit # 76543210 bit name timer bit 7 timer bit 6 timer bit 5 timer bit 4 timer bit 3 timer bit 2 timer bit 1 timer bit 0 read/write rrrrrrrr reset 00000000 figure 11-1. timer lsb register [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 24 of 51 timer msb address 0x25 bit [3:0]: timer higher nibble bit [7:4]: reserved 12.0 i 2 c and hapi configuration register internal hardware supports communication with exte rnal devices through two interfaces: a two-wire i 2 c-compatible interface, and a hapi for 1, 2, or 3 byte transfers. the i 2 c-compatible interface and hapi functions, discussed in detail in sections 13.0 and 14.0, share a common configuration register (see figure 12-1 ). all bits of this register are cleared on reset. i 2 c configuration address 0x09 note: i 2 c-compatible function must be separately enabled as described in section 13.0. bits [7,1:0] of the hapi/i 2 c configuration register c ontrol the pin out configur ation of the hapi and i 2 c-compatible interfaces. bits [5:2] are used in hapi mode on ly, and are described in section 14.0. table 12-1 shows the hapi por t configurations, and table 12-2 shows i 2 c pin location configuration options. these i 2 c-compatible options exist due to pin limitations in certain packages, and to allow simultaneous hapi and i 2 c-compatible operation. hapi operation is enabled whenever either hapi port width bit (bit 1 or 0) is non-zero. this affects gpio operation as describe d in section 14.0. i 2 c-compatible blocks must be separately enabled as de scribed in se ction 13.0. bit # 76543210 bit name reserved reserved reserved reserved timer bit 11 timer bit 10 timer bit 9 timer bit 8 read/write ----rrrr reset 00000000 figure 11-2. timer msb register figure 11-3. timer block diagram bit # 76543210 bit name i 2 c position reserved lempty polarity drdy polarity latch empty data ready hapi port width bit 1 hapi port width bit 0 read/write r/w - r/w r/w r r r/w r/w reset 00000000 figure 12-1. hapi/i 2 c configuration register 10 9 7 8 5 6432 1-mhz clock 1.024-ms interrupt 128- s interrupt to timer register 8 1 0 11 l1 l0 l2 l3 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 25 of 51 13.0 i 2 c-compatible controller the i 2 c-compatible block provides a versatile two-wire communication with external devices, supporting master, slave, and multi- master modes of operation. the i 2 c-compatible block functions by handling the low-level signaling in hardware, and issuing interrupts as needed to allow firmware to take appropriate action during transactions. while waiting for firmware response, the hardware keeps the i 2 c-compatible bus idle if necessary. the i 2 c-compatible block generates an interrupt to the microcontro ller at the end of each received or transmitted byte, when a stop bit is detected by the slave when in re ceive mode, or when arbitratio n is lost. details of the interrupt responses are giv en in section 16.8 . the i 2 c-compatible interface consists of two registers, an i 2 c data register ( figure 13-1 ) and an i 2 c status and control register ( figure 13-2 ). the data register is implemented as separa te read and write registers. generally, the i 2 c status and control register should only be monitored after the i 2 c interrupt, as all bits are valid at that ti me. polling this register at other times could read misleading bit status if a transaction is underway. the i 2 c scl clock is connected to bit 0 of gpio port 1 or gpio port 2, and the i 2 c sda data is connected to bit 1 of gpio port 1 or gpio port 2. refer to section 12.0 for t he bit definitions and functionality of the hapi/i 2 c configuration register, which is used to set the locations of the configurable i 2 c-compatible pi ns. once the i 2 c-compatible functionality is enabled by setting bit 0 of the i 2 c status & control register, the two l sb bits ([1:0]) of the corresponding gpio port are placed in open drain mode, regardless of the settings of the gp io configuration register.the elec trical characteristics of the i 2 c-compatible interface is the same as that of gpio ports 1 and 2. note that the i ol (max) is 2 ma @ v ol = 2.0 v for ports 1 and 2. all control of the i 2 c clock and data lines is performed by the i 2 c-compatible block. i 2 c data address 0x29 bits [7..0] : i 2 c data contains the 8 bit data on the i 2 c bus i 2 c status and control the i 2 c status and control register bits are defined in table 14-1 , with a more detailed description following. table 12-1. hapi port configuration port width (bits[1:0]) hapi port width 11 24 bits: p3[7:0], p1[7:0], p0[7:0] 10 16 bits: p1[7:0], p0[7:0] 01 8 bits: p0[7:0] 00 no hapi interface table 12-2. i 2 c port configuration i 2 c position (bit[7]) port width (bit[1]) i 2 c position x1i 2 c on p2[1:0], 0:scl, 1:sda 00i 2 c on p1[1:0], 0:scl, 1:sda 10i 2 c on p2[1:0], 0:scl, 1:sda bit # 76543210 bit name i 2 c data 7 i 2 c data 6 i 2 c data 5 i 2 c data 4 i 2 c data 3 i 2 c data 2 i 2 c data 1 i 2 c data 0 read/write r/wr/wr/wr/wr/wr/wr/wr/w reset xxxxxxxx figure 13-1. i 2 c data register bit # 76543210 bit name mstr mode continue/busy xmit mode ack addr arb lost/restart received stop i 2 c enable read/write r/wr/wr/wr/wr/wr/wr/wr/w reset 00000000 figure 13-2. i 2 c status and control register [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 26 of 51 bit 7 : mstr mode setting this bit to 1 causes the i 2 c-compatible block to initiate a master mode transaction by sending a start bit and transmitting the first data byte from the data register (this ty pically holds the target address and r/w bit). subsequent bytes are initiated by setting the continue bit, as described below. clearing this bit (set to 0) causes the gpio pins to operate normally in master mode, the i 2 c-compatible block generates the clock (sck), an d drives the data line as required depending on transmit or receive state. the i 2 c-compatible block performs any required ar bitration and clock syn chronization. in the event of a loss of arbitration, this mstr bit is cleared, the arb lost bit is set, and an interrupt is generated by the microcontroller. if the chip is the target of an external mast er that wins arbitration, then the interrupt is held off until th e transaction from the exter nal master is completed. when mstr mode is cleared from 1 to 0 by a firmware write, an i 2 c stop bit is generated. bit 6 : continue / busy this bit is written by the firmware to indi cate that the firmware is r eady for the next byte transact ion to begin. in other wor ds, the bit has responded to an interrupt request and has completed the required update or read of the data register. during a read this bit indicates if the hardware is busy and is locking out additional writes to the i 2 c status and control register. this locking allows the hardware to complete certain operations that may require an extended period of time. following an i 2 c interrupt, the i 2 c-compatible block does not return to the busy state until firmware sets the continue bit. this allows the firmware to make one control register write without the need to check the busy bit. bit 5 : xmit mode this bit is set by firmware to enter transmit mode and perf orm a data transmit in master or slave mode. clearing this bit sets the part in receive mode. firmware generally determines the value of this bit from the r/w bit associated with the i 2 c address packet. the xmit mode bit state is ignored when initially writing the mstr mode or the restart bits, as these cases always cause transmit mode for the first byte. bit 4 : ack this bit is set or cleared by firmware during receive operat ion to indicate if the hardware should generate an ack signal on the i 2 c-compatible bus. writing a 1 to this bit generates an ack (sda low) on the i 2 c-compatible bus at the ack bit time. during transmits (xmit mode = 1), this bit should be cleared. bit 3 : addr this bit is set by the i 2 c-compatible block during the first byte of a slave receive transaction, after an i 2 c start or restart. the addr bit is cleared when the firmware sets the continue bi t. this bit allows the firmware to recognize when the master has lost arbitration, and in slave mode it allows the fi rmware to recognize that a start or restart has occurred. bit 2 : arb lost/restart this bit is valid as a status bit (arb lost) after master mode transactions. in master mo de, set this bit (along with the continue and mstr mode bits) to perform an i 2 c restart sequence. the i 2 c target address for the restart must be written table 13-1. i 2 c status and control register bit definitions bit name description 0i 2 c enable when set to ?1?, the i 2 c-compatible function is enabled. when cleared, i 2 c gpio pins operate normally. 1 received stop reads 1 only in slave receive mode, when i 2 c stop bit detected (unless firmware did not ack the last transaction). 2 arb lost/restart reads 1 to indicate master has lost ar bitration. reads 0 otherwise. write to 1 in master mode to perform a restart sequence (also set continue bit). 3 addr reads 1 during first byte after start/restar t in slave mode, or if master loses arbitration. reads 0 otherwise. this bit should always be written as 0. 4 ack in receive mode, write 1 to generate ack, 0 for no ack. in transmit mode, reads 1 if ack was received, 0 if no ack received. 5 xmit mode write to 1 for trans mit mode, 0 for receive mode. 6 continue/busy write 1 to indicate ready for next transaction. reads 1 when i 2 c-compatible block is busy with a transaction, 0 when transaction is complete. 7 mstr mode write to 1 for master mode, 0 for slave mode. this bit is cleared if master loses arbitration. clearing from 1 to 0 generates stop bit. [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 27 of 51 to the data register before setting the continue bit. to preven t false arb lost signals, the restart bit is cleared by hardware during the restart sequence. bit 1 : receive stop this bit is set when the slave is in receive mode and detects a stop bit on the bus. the receive stop bit is not set if the firmware terminates the i 2 c transaction by not acknowledging the previous byte transmitted on the i 2 c-compatible bus, e.g. in receive mode if firmware sets the continue bit and clears the ack bit. bit 0 : i 2 c enable set this bit to override gpio definition with i 2 c-compatible function on the two i 2 c-compatible pins. when this bit is cleared, these pins are free to function as gpios. in i 2 c-compatible mode, the two pins operate in open drain mode, independent of the gpio configuration setting. 14.0 hardware assisted parallel interface (hapi) the cy7c64x13c processor provides a hardware assisted parallel interface for bus widths of 8, 16, or 24 bits, to accommodate data transfer with an external microcontr oller or similar device. control bits for selecting the byte width are in the hapi/i 2 c configuration register ( figure 12-1 ), bits 1 and 0. signals are provided on port 2 to control the hapi interface. table 14-1 describes these signals and the hapi control bits in the hapi/i 2 c configuration register. enabling hapi causes the gpio se tting in the gpio configurat ion register (0x08) to be overridden. the port 2 output pins are in cmos output mode and port 2 input pins are in input mode (open drain mode with q3 off in figure 9-1 ). hapi read by external device from cy7c64x13c: in this case (see figure 24-3 ), firmware writes data to the gpio ports. if 16-b it or 24-bit transfers ar e being made, port 0 should be written last, since writes to port 0 asserts the data ready bi t and the dready pin to signal the external device that data i s available. the external device then drives the oe and cs pins active (low), which causes the hapi data to be output on the port pins. when oe is returned high (inactive), the hapi/gpio interrupt is ge nerated. at that point, firmwar e can reload the hapi latches for the next output, again writing port 0 last. the data ready bit reads the opposite state from the external dreadypin on pin p2[3]. if the drdy polarity bit is 0, dreadypin is active high, and the data ready bit is active low. hapi write by external device to cy7c64x13c: in this case (see figure 24-4 ), the external device drives the stb and cs pins active (low) when it drives new data onto the port pins. when this happens, the internal latches become full , which causes the lat ch empty bit to be deasserted. when stb is returned high (inactive), the hapi/gpio interrupt is gener ated. firmware then reads the parallel ports to empty the hapi latches. if 16-bit or 24-bit transfers are being made, port 0 sh ould be read last because reads from port 0 assert the latch em pty bit and the latemptypin to signal the external device for more data. the latch empty bit reads the opposite state from the external latemptypin on pin p2 [2]. if the lempty polarity bit is 0, latemptypin is active high, and t he latch empty bit is active low. table 14-1. port 2 pin and hapi configuration bit definitions pin name direction description (port 2 pin) p2[2] latemptypin out ready for more input data from external interface. p2[3] dreadypin out output data ready for external interface. p2[4] stb in strobe signal for latching incoming data. p2[5] oe in output enable, causes chip to output data. p2[6] cs in chip select (gates stb and oe ). bit name r/w description (hapi/i 2 c configuration register) 2 data ready r asserted after firmware writes data to port 0, until oe driven low. 3 latch empty r asserted after firmware reads data from port 0, until stb driven low. 4 drdy polarity r/w determines polarity of data ready bit and dreadypin: if 0, data ready is active low, dreadypin is active high. if 1, data ready is active hi gh, dreadypin is active low. 5 lempty polarity r/w determines polarity of latch empty bit and latemptypin: if 0, latch empty is active low, latemptypin is active high. if 1, latch empty is active high, latemptypin is active low. [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 28 of 51 15.0 processor status and control register processor status and control address 0xff bit 0: run this bit is manipulated by the halt inst ruction. when halt is executed, all the bi ts of the processor status and control register are cleared to 0. since the run bi t is cleared, the processor stops at the end of the curr ent instruction. the process or remains halted until an appropriate reset occurs (power-on or watchdog). this bit should normally be written as a ?1.? bit 1: reserved bit 1 is reserved and must be written as a zero. bit 2: interrupt enable sense this bit indicates whether interrupts are enabled or disabled. fi rmware has no direct control over this bit as writing a zero or one to this bit position has no effect on interrupts. a ?0? indicates that interrupts are masked off and a ?1? indicates tha t the interrupts are enabled. this bit is further gated with the bit settings of the global interrupt enable register ( figure 16- 1 ) and usb end point interrupt enable register ( figure 16-2 ). instructions di, ei, and reti manipulate the state of this bit. bit 3: suspend writing a ?1? to the suspend bit halts the processor and cause the microcontroller to enter t he suspend mode that signifi- cantly reduces power consumption. a pending, enabled interrup t or usb bus activity causes the device to come out of suspend. after coming out of suspend, the device resumes fi rmware execution at the instruction following the iowr which put the part into suspend. an iowr attempting to put the part into suspend is ignored if usb bus activity is present. see section 8.0 for more details on suspend mode operation. bit 4: power-on reset the power-on reset is set to ?1? during a power-on reset. th e firmware can check bits 4 and 6 in the reset handler to determine whether a reset was caused by a power-on conditi on or a watchdog timeout. a por event may be followed by a watchdog reset before firmware begins executing, as explained below. bit 5: usb bus reset interrupt the usb bus reset interrupt bit is set when the usb bus reset is detected on receiving a usb bus reset signal on the upstream port. the usb bus reset signal is a single-ended zero (se0) that lasts from 12 to 16 s. an se0 is defined as the condition in which both the d+ line and the d? line are low at the same time. bit 6: watchdog reset the watchdog reset is set during a reset initiated by the wa tchdog timer. this indicates the watchdog timer went for more than t watch (8 ms minimum) between watchdog clears. this can occur with a por event, as noted below. bit 7: irq pending the irq pending, when set, indicates that one or more of th e interrupts has been recognized as active. an interrupt remains pending until its interrupt enable bit is set ( figure 16-1 , figure 16-2 ) and interrupts are globally enabled. at that point, the internal interrupt handling sequence clears this bi t until another interrupt is detected as pending. during power-up, the processor status and control register is se t to 00010001, which indicates a por (bit 4 set) has occurred and no interrupts are pending (bit 7 clear). during the 96 ms suspend at start-up (explained in section 7.1), a watchdog reset also occurs unless this suspend is aborted by an upstream se0 before 8 ms. if a wdr occurs during the power-up suspend interval, firmware reads 01010001 from the st atus and control register after power-up. normally, the por bit should be cleared so a subsequent wdr can be clearly identified. if an upstream bus reset is received be fore firmware examines this register, the bus reset bit may also be set. during a watchdog reset, the processor status and control register( figure 15-1 ) is set to 01xx0001b, which indicates a watchdog reset (bit 6 set) has occurred and no interrupts are pending (bit 7 clear). the watchdog reset does not effect the state of the por and the bus reset interrupt bits. bit # 76543210 bit name irq pending watchdog reset usb bus reset interrupt power-on reset suspend interrupt enable sense reserved run read/write r r/w r/w r/w r/w r r/w r/w reset 00010001 figure 15-1. processor status and control register [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 29 of 51 16.0 interrupts interrupts are generated by the gpio/d ac pins, the internal timers, i 2 c-compatible interface or hapi operation, or on various usb traffic conditions. all interrupts are maskable by the global interrupt enable register and the usb end point interrupt ena ble register. writing a ?1? to a bit position enables th e interrupt associated with that bit position. global interrupt enable register address 0x20 bit 0 : usb bus rst interrupt enable 1= enable interrupt on a usb bus reset; 0 = disable interrupt on a usb bus reset (refer to section 16.3) bit 1 :128-s interrupt enable 1 = enable timer interrupt every 128 s; 0 = disable timer interrupt for every 128 s. bit 2 : 1.024-ms interrupt enable 1= enable timer interrupt every 1.024 ms; 0 = disable timer interrupt every 1.024 ms. bit 3 : reserved bit 4 : dac interrupt enable 1 = enable dac interrupt; 0 = disable dac interrupt bit 5 : gpio interrupt enable 1 = enable interrupt on falling/rising edge on any gpio; 0 = disable interrupt on falling/rising edge on any gpio (refer to section 14.7, 9.1 and 9.2.) bit 6 : i 2 c interrupt enable 1= enable interrupt on i2c related activity; 0 = disable i2c related activity interrup t. (refer to section 16.8). bit 7 : reserved usb endpoint interrupt enable address 0x21 bit 0 : epa0 interrupt enable 1= enable interrupt on data activity through endpoint a0; 0= disable interrupt on data activity through endpoint a0 bit 1 : epa1 interrupt enable 1= enable interrupt on data activity through endpoint a1; 0= disable interrupt on data activity through endpoint a1 bit 2 : epa2 interrupt enable 1= enable interrupt on data activity through endpoint a2; 0= disable interrupt on data activity through endpoint a2. bit 3 : epb0 interrupt enable 1= enable interrupt on data activity through endpoint b0; 0= disable interrupt on data activity through endpoint b0 bit 4 : epb1 interrupt enable 1= enable interrupt on data activity through endpoint b1; 0= disable interrupt on data activity through endpoint b1 bit [7..5] : reserved during a reset, the contents the global interrupt enable regi ster and usb end point interrupt enable register are cleared, effectively, disabling all interrupts bit # 76543210 bit name reserved i 2 c interrupt enable gpio interrupt enable dac interrupt enable reserved 1.024-ms interrupt enable 128- s interrupt enable usb bus rst interrupt enable read/write - r/w r/w - r/w r/w r/w r/w reset - 00x0000 figure 16-1. global interrupt enable register bit # 76543210 bit name reserved reserved reserved epb1 interrupt enable epb0 interrupt enable epa2 interrupt enable epa1 interrupt enable epa0 interrupt enable read/write - - - r/w r/w r/w r/w r/w reset - - - 00000 figure 16-2. usb endpoint interrupt enable register [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 30 of 51 the interrupt controller contains a separate flip-flop for each interrupt. see figure 16-3 for the logic block diagram of the interrupt controller. when an interrupt is generated, it is first registered as a pending interru pt. it stays pending until it is service d or a reset occurs. a pending interrupt only generates an interrupt request if it is enabled by the corresponding bit in the interrupt enab le registers. the highest priority interrupt request is serviced following the completion of the cu rrently executing instruction. when servicing an interrupt, the hardware does the following 1. disables all interrupts by clearing the global interrupt enable bit in the cpu (the state of this bit can be read at bit 2 of the processor status and control register, figure 15-1 ). 2. clears the flip-flop of the current interrupt. 3. generates an automatic call instruction to the rom address associ ated with the interrupt being serviced (i.e., the interrupt vector, see section 16.1). the instruction in the interrupt table is typically a jmp instru ction to the address of the interrupt service routine (isr). th e user can re-enable interrupts in the interrupt service routine by execut ing an ei instruction. interrupts can be nested to a level l imited only by the available stack space. the program counter value as well as the carry and zero flags (cf, zf) are stored onto the program stack by the automatic call instruction generated as part of the interrupt acknowledge pr ocess. the user firmware is responsible for ensuring that the processor state is preserved and restored during an interrupt. the push a instruction should typically be used as the first command in the isr to save th e accumulator value and the pop a instruction s hould be used to restore the accumulator value just before the reti instruct ion. the program counter cf and zf are restored and interrupts are enabled when the reti instruction is executed. the di and ei instructions can be used to disable and enable interrupts, respectively. these instructions affect only the globa l interrupt enable bit of the cpu. if desir ed, ei can be used to re-enable interrupts wh ile inside an isr, instead of waiting for the reti that exists the isr. while the global interrupt enable bit is cleared, the presence of a pending interrupt can be detected by examining the irq sense bit (bit 7 in the processor status and control register). 16.1 interrupt vectors the interrupt vectors supported by the usb controller are listed in table 16-1 . the lowest-numbered interrupt (usb bus reset interrupt) has the highest priority, and the highest-numbered interrupt (i 2 c interrupt) has the lowest priority. although reset is not an interrupt, the first instruction ex ecuted after a reset is at prom address 0x0000h?which corresponds to the first entry in the interrupt vector table. because the jmp instruction is two bytes long, the interrupt vectors occupy t wo bytes. clr global interrupt interrupt acknowledge irqout usb reset clear interrupt interrupt priority encoder enable [0] d q 1 enable bit clr usb reset irq 128- s clr 128- s irq 1-ms clr 1-ms irq addra ep0 irq addra ep0 clr i 2 c irq vector enable [6] clk clr d q clk 1 i 2 c clr i 2 c int usb reset int addra ep1 irq addra ep1 clr irq sense irq controlled by di, ei, and reti instructions dac irq dac clr to cpu cpu gpio irq gpio clr hub irq hub clr addra ep2 irq addra ep2 clr addrb ep0 irq addrb ep0 clr addrb ep1 irq addrb ep1 clr (reg 0x20) (reg 0x20) clr enable [2] d q 1 clk addra enp2 int (reg 0x21) int enable sense figure 16-3. interrupt cont roller function diagram [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 31 of 51 16.2 interrupt latency interrupt latency can be calculated from the following equation: interrupt latency = (number of clock cycles remaining in the current inst ruction) + (10 clock cycles for the call instruction) + (5 clock cycles for the jmp instruction) for example, if a 5 clock cycle instruction such as jc is being executed when an interrupt occurs, the first instruction of the interrupt service routine executes a mini mum of 16 clocks (1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt is issued. for a 12-mhz internal clock (6-mhz crystal), 20 clock periods is 20 / 12 mhz = 1.667 s. 16.3 usb bus reset interrupt the usb controller recognizes a usb reset when a single ended zero (se0) condition persists on the upstream usb port for 12?16 s (the reset may be recognized for an se0 as short as 12 s, but is always recognized for an se0 longer than 16 s). se0 is defined as the condition in which bot h the d+ line and the d? line are low. bit 5 of the status and control register is set to record this event. the interrupt is asserted at the end of the bus reset. if the usb reset occurs during the start-up delay following a por, the delay is aborted as described in section 7. 1. the usb bus reset interrupt is generated when the se0 state is deasserted. a usb bus reset clears the following registers: sie section:usb device addr ess registers (0x10, 0x40) 16.4 timer interrupt there are two periodic timer interrupts: the 128- s interrupt an d the 1.024-ms interrupt. the user should disable both timer interrupts before going into the suspend mode to avoid possible conflicts between servicing the timer interrupts first or the s uspend request first. 16.5 usb endpoint interrupts there are five usb endpoint interrupts, one per endpoint. a usb endpoint interrupt is generated after the usb host writes to a usb endpoint fifo or after the usb controller sends a packet to the usb host. the interrupt is generated on the last packet of the transaction (e.g., on the host?s ack during an in, or on th e device ack during on out). if no ack is received during an in transaction, no interrupt is generated. 16.6 dac interrupt each dac i/o pin can generate an interrupt, if enabled. the interrupt polarity for each dac i/o pin is programmable. a positive polarity is a rising edge input while a negative polarity is a fa lling edge input. all of the dac pins share a single interrupt vector, which means the firmware needs to read the dac port to determine which pin or pins caused an interrupt. if one dac pin has triggered an interrupt, no other dac pins can cause a dac interrupt until that pin has returned to its inact ive (non-trigger) state or the corresponding interrupt enable bit is cleared. the usb controller does not assign interrupt priority to different dac pins and the dac interrupt enable register is not cleared during the interrupt acknowledge process. table 16-1. interrupt vector assignments interrupt vector number rom address function not applicable 0x0000 execution after reset begins here 1 0x0002 usb bus reset interrupt 2 0x0004 128- s timer interrupt 3 0x0006 1.024-ms timer interrupt 4 0x0008 usb address a endpoint 0 interrupt 5 0x000a usb address a endpoint 1 interrupt 6 0x000c usb address a endpoint 2 interrupt 7 0x000e usb address a endpoint 3 interrupt 8 0x0010 usb address a endpoint 4 interrupt 9 0x0012 reserved 10 0x0014 dac interrupt 11 0x0016 gpio interrupt 12 0x0018 i 2 c interrupt [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 32 of 51 16.7 gpio/hapi interrupt each of the gpio pins can generate an interrupt, if enabled. the interrupt polarity can be programmed for each gpio port as part of the gpio configuration. all of the gpio pins share a single interrupt vector, which means the firmware needs to read th e gpio ports with enabled interrupts to determine which pin or pi ns caused an interrupt. a block diagram of the gpio interrupt logic is shown in figure 16-4 . refer to sections 9.1 and 9.2 for more informati on of setting gpio interrupt polarity and enabling individual gpio interrupts. if one port pin has triggered an interrupt, no other port pins c an cause a gpio interrupt until t hat port pin has returned to i ts inactive (non-trigger) state or its corresponding port interrupt enable bi t is cleared. the usb controller does not assign interrupt pri ority to different port pins and the port interrupt enable regist ers are not cleared during the interrupt acknowledge process. when hapi is enabled, the hapi logic takes over the interrupt vector and blocks any interrupt from the gpio bits, including ports/bits not being used by hapi . operation of the hapi interrupt is independent of the gpio sp ecific bit interrupt enables, a nd is enabled or disabled only by bit 5 of the global interrupt enable register ( figure 16-1 ) when hapi is enabled. the settings of the gpio bit interrupt enables on ports/bits not used by hapi stil l effect the cmos mode operatio n of those ports/bits. the eff ect of modifying the interrupt bits while the port config bits are set to ?10? is shown in table 9-1 . the events that generate hapi interrupts are described in section 14.0. 16.8 i 2 c interrupt the i 2 c interrupt occurs after various events on the i 2 c-compatible bus to signal the need for firmware interaction. this generally involves reading the i 2 c status and control register ( figure 13-2 ) to determine the cause of the interrupt, loading/reading the i 2 c data register as appropriate, and finally writing the status and control register to initiate the subseq uent transaction. the interrupt indicates that status bits are stabl e and it is safe to read and write the i 2 c registers. refer to section 13.0 for details on the i 2 c registers. when enabled, the i 2 c-compatible state machines generate interrupts on co mpletion of the following co nditions. the referenced bits are in the i 2 c status and control register. 1. in slave receive mode, after the slave receives a byte of data: the addr bit is set, if this is the first byte since a start or restart signal was sent by the external master. firmware must read or write the data regist er as necessary, then set the ack, xmit mode, and continue/busy bits appropriately for the next byte. 2. in slave receive mode, after a stop bit is detected: the received stop bit is set, if the stop bit fo llows a slave receive transaction where the ack bit was cleared to 0, no stop bit detection occurs. 3. in slave transmit mode, after the slave transmits a byte of data: the ack bit indicates if the master that requested the byte acknowledged the byte. if more bytes are to be sent, firmware writes the next byte into the data register and then sets the xmit mode and continue/busy bits as required. 4. in master transmit mode, after the master sends a byte of data. firmwa re should load the data register if necessary, and set the xmit mode, mstr mode , and continue/busy bits appropriately. clearing the mstr mode bit issues a stop signal to the i 2 c-compatible bus and return to the idle state. figure 16-4. gpio interrupt structure port register or gate gpio interrupt flip flop clr gpio pin 1 = enable 0 = disable port interrupt enable register 1 = enable 0 = disable interrupt priority encoder irqout interrupt vector d q m u x 1 (1 input per gpio pin) global gpio interrupt enable (bit 5, register 0x20) ira configuration [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 33 of 51 5. in master receive mode, after the master receives a byte of data: firmware should read the data and set the ack and continue/busy bits appropriately for the next byte. clearing the mstr mode bit at the same time causes the master state machine to issue a stop signal to the i 2 c-compatible bus and leave the i 2 c-compatible hardware in the idle state. 6. when the master loses arbitration: this condition clears the mstr mode bit and sets the arb lost/restart bit immediately and then waits for a stop signal on the i 2 c-compatible bus to generate the interrupt. the continue/busy bit is cleared by hardware prior to interrupt conditions 1 to 4. once the data register has been read or written, firmware should configure the other control bits and set the continue/busy bit for subsequent transactions. following an interrupt from master mode, firmware should perform only one wr ite to the status and contro l register that sets the continue/busy bit, without checking the value of the continue/busy bit. the busy bit may otherwise be active and i 2 c register contents may be changed by the hardware during the transaction, until the i 2 c interrupt occurs. 17.0 usb overview the usb hardware consists of the logic for a full-speed usb po rt. the full-speed serial interf ace engine (sie) interfaces the microcontroller to the usb bus. an external series resistor (r ext ) must be placed in series with the d+ and d? lines, as close to the corresponding pins as possible, to meet the u sb driver requirements of the usb specifications. 17.1 usb serial interface engine (sie) the sie allows the cy7c64x13c microcontroller to communicate with the usb host. the sie simplifies the interface between the microcontroller and usb by incorporating hardware that handl es the following usb bus activity independently of the micro- controller: ? bit stuffing/unstuffing ? checksum generation/checking ? ack/nak/stall ? token type identification ? address checking firmware is required to handle the following usb interface tasks: ? coordinate enumeration by responding to setup packets ? fill and empty the fifos ? suspend/resume coordination ? verify and select data toggle values 17.2 usb enumeration the usb device is enumerated under firmware control. the followi ng is a brief summary of the typical enumeration process of the cy7c64x13c by the usb host. for a detailed description of the enumeration process, refe r to the usb specification. in this description, ?firmware? refers to em bedded firmware in the cy7c64x13c controller. 1. the host computer sends a setup packet followed by a da ta packet to usb address 0 requesting the device descriptor. 2. firmware decodes the request and retrieves its de vice descriptor from the program memory tables. 3. the host computer performs a control read sequence and firmwar e responds by sending the device descriptor over the usb bus, via the on-chip fifos. 4. after receiving the descriptor, the host sends a setup packet followed by a data packet to address 0 assigning a new usb address to the device. 5. firmware stores the new address in its usb device addre ss register after the no-data control sequence completes. 6. the host sends a request for the device descriptor using the new usb address. 7. firmware decodes the request and retrieves the device descriptor from program memory tables. 8. the host performs a control read sequence and firmware resp onds by sending its device descriptor over the usb bus. 9. the host generates control reads from the device to request the configuration and report descriptors. 10.once the device receives a set configurat ion request, its functions may now be used. 17.3 usb upstream port status and control usb status and control is regulated by the usb status and control register, as shown in figure 17-1 . all bits in the register are cleared during reset. [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 34 of 51 usb status and control address 0x1f bits[2..0] : control action set to control action as per table 17-1 .the three control bits allow the upstream port to be driven manually by firmware. for normal usb operation, all of these bits must be cleared. table 17-1 shows how the control bits affect the upstream port. bit 3 : bus activity this is a ?sticky? bit that indicates if any non-idle usb event has occurred on the upstream usb port. firmware should check and clear this bit periodically to de tect any loss of bus activity. writing a ?0 ? to the bus activity bit clears it, whil e writing a ?1? preserves the current value. in other words, the firmware can clear the bus activity bit, but only the sie can set it. bits 4 and 5 : d? upstream and d+ upstream these bits give the state of each upstream port pin individually: 1 = high, 0 = low. bit 6 : endpoint mode this bit used to configure the number of usb endpoints. see section 18.2 for a detailed description. bit 7 : endpoint size this bit used to configure the number of usb endpoints. see section 18.2 for a detailed description. 18.0 usb serial interface engine operation usb device address a includes up to five endpoints: epa0, epa1, epa2, epa3, and epa4. endpoint (epa0) allows the usb host to recognize, set-up, and control the device. in particular , epa0 is used to receive and transmit control (including set-u p) packets. 18.1 usb device address the usb controller provides one usb device address with five endpoints. the usb device address register contents are cleared during a reset, setting the usb device address to zero and marking this address as disabled. figure 18-1 shows the format of the usb address registers. usb device address addresses 0x10 bit # 76543210 bit name endpoint size endpoint mode d+ upstream d? upstream bus activity control action bit 2 control action bit 1 control action bit 0 read/write r/w r/w r r r/w r/w r/w r/w reset 00000000 figure 17-1. usb status and control register table 17-1. control bit de finition for upstream port control bits co ntrol action 000 not forcing (sie controls driver) 001 force d+[0] high, d?[0] low 010 force d+[0] low, d?[0] high 011 force se0; d+[0] low, d?[0] low 100 force d+[0] low, d?[0] low 101 force d+[0] hiz, d?[0] low 110 force d+[0] low, d?[0] hiz 111 force d+[0] hiz, d?[0] hiz bit # 76543210 bit name device address enable device address bit 6 device address bit 5 device address bit 4 device address bit 3 device address bit 2 device address bit 1 device address bit 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 figure 18-1. usb device address registers [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 35 of 51 bits[6..0] :device address firmware writes this bits during the usb enumeration process to the non-zero address assigned by the usb host. bit 7 :device address enable must be set by firmware before the sie can resp ond to usb traffic to the device address. bit 7 (device address enable) in the usb device address regist er must be set by firmware bef ore the sie can respond to usb traffic to this address. the device addresses in bits [6:0] ar e set by firmware during the usb enumeration process to the non- zero address assigned by the usb host. 18.2 usb device endpoints the cy7c64x13c controller supports one usb device address and five endpoints for communication with the host. the config- uration of these endpoints, and associated fi fos, is controlled by bits [7,6] of the usb status and control register (0x1f). bi t 7 controls the size of the endpoints and bit 6 controls the numb er of endpoints. these configuration options are detailed in table 18-1 . the ?unused? fifo areas in the following table can be used by the firmware as additional user ram space. when the sie writes data to a fifo, the inte rnal data bus is driven by the sie; not the cpu. this causes a short delay in the cpu operation. the delay is thre e clock cycles per byte. for example, an 8-byte data write by the sie to the fifo generates a delay of 2 s (3 cycles/byte * 83.33 ns/cycle * 8 bytes). 18.3 usb control endpoint mode register all usb devices are required to have a control endpoint 0 (epa0) that is used to initialize and control each usb address. endpo int 0 provides access to the device configuration information and allows generic usb status and control accesses. endpoint 0 is bidirectional to both receive and transmit data. the other endpoi nts are unidirectional, but selectable by the user as in or ou t endpoints. the endpoint mode register is cleared during reset. the endpoint zero epa0 mode register uses the format shown in figure 18-2 . usb device endpoint zero mode addresses 0x12) bits[3..0] : mode these sets the mode which control how the control endpoint responds to traffic. bit 4 : ack this bit is set whenever the sie engages in a transaction to the register?s endpoint that completes with an ack packet. bit 5: endpoint 0 out received 1= token received is an out token. 0= token received is not an ou t token. this bit is set by the sie to report the type of token received by the corresponding device address is an out tok en. the bit must be cleared by firmware as part of the usb processing. table 18-1. memory allocation for endpoints usb status and control register (0x1f) bits [7, 6] [0,0] [1,0] [0,1] [1,1] label start address size label start address size label start address size label start address size unused 0xd8 8 unused 0xa8 8 epa4 0xd8 8 epa4 0xb0 8 unused 0xe0 8 unused 0xb0 8 epa3 0xe0 8 epa3 0xa8 8 epa2 0xe8 8 epa0 0xb8 8 epa2 0xe8 8 epa0 0xb8 8 epa1 0xf0 8 epa1 0xc0 32 epa1 0xf0 8 epa1 0xc0 32 epa0 0xf8 8 epa2 0xe0 32 epa0 0xf8 8 epa2 0xe0 32 bit # 76543210 bit name endpoint 0 setup received endpoint 0 in received endpoint 0 out received ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 figure 18-2. usb device endpoint zero mode registers [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 36 of 51 bit 6: endpoint 0 in received 1= token received is an in token. 0= token received is not an in token. this bit is set by the sie to report the type of token received by the corresponding device address is an in token. the bit must be cleared by firmware as part of the usb processing. bit 7: endpoint 0 setup received 1= token received is a setup token. 0= token received is not a setup token. this bit is set only by the sie to report the type of token received by the corresponding device address is a setup token. any write to this bit by the cpu will clear it (set it to 0). the bit is forced high from the start of the data packet phase of the setup transaction until the start of the ack packet returned by the sie. the cpu should not cl ear this bit during this interval, and subsequently, until the cpu first does an iord to this endpoint 0 mode register. the bit must be cleared by firmware as part of the usb processing. bits[6:0] of the endpoint 0 mode register are locked from cpu write operations whenever the si e has updated one of these bits, which the sie does only at the end of the token phase of a tran saction (setup... data... ack, ou t... data... ack, or in... data ... ack). the cpu can unlock these bits by doing a subsequent read of this register. only endpoint 0 mode registers are locked when updated. the locking mechanism does not a pply to the mode registers of other endpoints. because of these hardware locking features, firmware must perform an iord after an iowr to an endpoint 0 register. this verifie s that the contents have changed as desired, and that the sie has not updated these values. while the setup bit is set, the cpu cannot wr ite to the endpoint zero fifos. this prev ents firmware from overwriting an incomin g setup transaction before firmware has a ch ance to read the setup data. refer to table 18-1 for the appropriate endpoint zero memory locations. the mode bits (bits [3:0]) control how the endpoint respond s to usb bus traffic. the mode bit encoding is shown in table 19-1 . additional information on the mode bits can be found in table 19-2 . 18.4 usb non-control endpoint mode registers the format of the non-control endpoint mode register is shown in figure 18-3 . usb non-control device endpoint mode addresses 0x14, 0x16, 0x42 , 0x44 bits[3..0] : mode these sets the mode which control how t he control endpoint responds to traffic. the mode bit encoding is shown in table 19-1 bit 4 : ack this bit is set whenever the sie engages in a transaction to the register?s endpoint that completes with an ack packet. bits[6..5] : reserved must be written zero during register writes. bit 7 : stall if this stall is set, the sie stalls an out packet if the mode bits are set to ack-in, and the sie stalls an in packet if the mode bits are set to ack-out. for all other modes, the stall bit must be a low. 18.5 usb endpoint counter registers there are five endpoint counter registers, with identical formats for both control and non-control endpoints. these registers contain byte count information for usb transactions, as well as bits for data packet status. the format of these registers is s hown in figure 18-4 : usb endpoint counter addresses 0x11, 0x13, 0x15, 0x41, 0x43 bit # 76543210 bit name stall reserved reserved ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 figure 18-3. usb non-control de vice endpoint mode registers bit # 76543210 bit name data 0/1 toggle data valid byte count bit 5 byte count bit 4 byte count bit 3 byte count bit 2 byte count bit 1 byte count bit 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 figure 18-4. usb endpoint counter registers [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 37 of 51 bits[5..0] : byte count these counter bits indicate the number of data bytes in a tran saction. for in transactions, firmware loads the count with the number of bytes to be transmitted to the host from the end point fifo. valid values are 0 to 32, inclusive. for out or setup transactions, the count is updated by hardware to t he number of data bytes received, plus 2 for the crc bytes. valid values are 2 to 34, inclusive. bit 6 : data valid this bit is set on receiving a proper crc when the endpoint fifo buffer is loaded with data during transactions. this bit is used out and setup tokens only. if the crc is not correct, t he endpoint interrupt occurs, but data valid is cleared to a zero. bit 7 : data 0/1 toggle this bit selects the data packet?s toggle state: 0 for data0, 1 for data1. for in transactions, firmware must set this bit to the desired state. for out or setup transactions, the hardware sets this bit to the state of the received data toggle bit. whenever the count u pdates from a setup or out transaction on endpoint 0, the counter register locks and cannot be written by the cpu. reading the register unlocks it. this prevents firmwar e from overwriting a status update on incoming setup or out transactions before firmware has a chance to read the data. on ly endpoint 0 counter register is locked when updated. the lockin g mechanism does not apply to the count registers of other endpoints. 18.6 endpoint mode/count registers update and locking mechanism the contents of the endpoint mode and counter registers ar e updated, based on the packet flow diagram in figure 18-5 . two time points, update and setup, are shown in the same fi gure. the following activities occur at each time point: setup: the setup bit of the endpoint 0 mode register is forced high at th is time. this bit is forced high by the sie until the end of the data phase of a control write tran sfer. the setup bit can not be cleared by firmware during this time. the affected mode and counter registers of endpoint 0 are lock ed from any cpu writes once they are updated. these registers can be unlocked by a cpu read, only if t he read operation occurs after the update. the firmware needs to perform a register read as a part of the endpoint isr processing to unlock the ef fected registers. the locking mechanism on mode and counter registers ensures that the firmware recognizes the changes that the sie might have made since the previous io read of that register. update: 1. endpoint mode register ? all the bits are updated (e xcept the setup bit of the endpoint 0 mode register). 2. counter registers ? all bits are updated. 3. interrupt ? if an interrupt is to be generated as a result of the transaction, the interr upt flag for the corresponding endpo int is set at this time. for details on what conditions are required to generate an endpoint interrupt, refer to table 19-2 . 4. the contents of the updated endpoint 0 mode and counter registers are locked, exc ept the setup bit of the endpoint 0 mode register which was locked earlier. [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 38 of 51 a c k 1. in token h o s t d e v i c e s y n c in a d d r c r c 5 e n d p s y n c d a t a 1/0 c r c 16 s y n c data token packet data packet hand shake packet update host to device device to host host to device s y n c in a d d r c r c 5 e n d p token packet host to device s y n c data packet device to host nak/stall update 2. out or setup token without crc error s y n c o u t / set up a d d r c r c 5 e n d p token packet host to device s y n c d a t a 1/0 c r c 16 data data packet host to device setup ack, nak, stal s y n c hand shake packet update device to host 3. out or setup token with crc error s y n c o u t / set up a d d r c r c 5 e n d p token packet host to device s y n c d a t a 1/0 c r c 16 data data packet host to device update only if fifo is written figure 18-5. token/data packet flow diagram [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 39 of 51 19.0 usb mode tables mode this lists the mnemonic given to the different modes that can be set in the endpoint mode register by writing to the lower nibb le (bits 0..3). the bit settings for different modes are covered in the column marked ?mode bits?. the status in and status out represent the status stage in the in or out transfer involving the control endpoint. mode bits these column lists the encoding for different modes by setting bi ts[3..0] of the endpoint mode register. this modes represents how the sie responds to different tokens s ent by the host to an endpoint. for instance, if the mode bits are set to ?0001? (nak in/out), the sie will respond with an ? ack on receiving a setup token from the host ? nak on receiving an out token from the host ? nak on receiving an in token from the host refer to section 13.0 for more information on the sie functioning setup, in and out these columns shows the sie?s response to the host on receiving a setup, in and out token depending on the mode set in the endpoint mode register. a ?check? on the out token column, implie s that on receiving an out token the si e checks to see whether the out packet is of zero length and has a data toggle (dtog) set to ?1.? if the dtog bit is set and the received out packet has zero length, the out is acked to complete the transaction. if either of this condition is not met the sie will respond with a stalll or just ign ore the transaction. a ?tx count? entry in the in column implies that the sie transm it the number of bytes specified in the byte count (bits 3..0 of the endpoint count register) to the host in response to the in token received. a ?tx0 byte? entry in the in column implies that the sie transmit a zero length byte packet in respon se to the in token receive d from the host. an ?ignore? in any of the columns means that the device will not send any handshake tokens (no ack) to the host. table 19-1. usb register mode encoding mode mode bits setup in out comments disable 0000 ignore ignore ignore ignore all usb traffic to this endpoint nak in/out 0001 accept nak nak forced from setu p on control endpoint, from modes other than 0000 status out only 0010 accept stall check for control endpoints stall in/out 0011 accept stall stall for control endpoints ignore in/out 0100 accept ignore ignore for control endpoints isochronous out 0101 ignore ignore always for isochronous endpoints status in only 0110 accept tx 0 byte stall for control endpoints isochronous in 0111 ignore tx count ignore for isochronous endpoints nak out 1000 ignore ignore nak is set by sie on an ack from mode 1001 (ack out) ack out(stall [3] =0) ack out(stall [3] =1) 1001 1001 ignore ignore ignore ignore ack stall on issuance of an ack this mode is changed by sie to 1000 (nak out) nak out - status in 1010 accept tx 0 byte nak is set by sie on an ack from mode 1011 (ack out- status in) ack out - status in 1011 accept tx 0 byte ack on issuance of an ack this mode is changed by sie to 1010 (nak out - status in) nak in 1100 ignore nak ignore is set by sie on an ack from mode 1101 (ack in) ack in(stall [3] =0) ack in(stall [3] =1) 1101 1101 ignore ignore tx count stall ignore ignore on issuance of an ack this mode is changed by sie to 1100 (nak in) nak in - status out 1110 accept nak check is set by sie on an ack from mode 1111 (ack in - status out) ack in - status out 1111 accept tx count check on issuance of an ack this mode is chan ged by sie to 1110 (nak in - status out) [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 40 of 51 an ?accept? in any of the columns means that the device will respond with an ack to a valid setup transaction tot he host. comments some mode bits are automatically changed by the sie in respons e to certain usb transactions. for example, if the mode bits [3:0] are set to '1111' which is ack in-status out mode as shown in table 22-1, the sie will change the endpoint mode bits [3:0 ] to nak in-status out mode (1110) after ack?ing a valid status stage out token. the firmware needs to update the mode for the sie to respond appropriately. see table 18-1 for more details on what modes will be changed by the sie. a disabled endpoint will remain disabled until changed by firmware, and all endpoints reset to the disabled mode (0000). firmware normally enables the endpoint mode after a setconfiguration request. any setup packet to an enabled endpoint with mode set to acc ept setups will be changed by the sie to 0001 (naking ins and outs). any mode set to accept a setup will send an ack handshake to a valid setup token. the control endpoint has three status bits for identifying the token type received ( setup, in, or out), but the endpoint must b e placed in the correct mode to function as such. non-control endpoints should not be placed into modes that accept setups. note that most modes that co ntrol transactions involving an ending ack, are ch anged by the sie to a corresponding mode which naks subsequent packets following the ack. exceptions are modes 1010 and 1110. note: the sie offers an ?ack out?status in? mode and not an ?ack out ?nak in? mode. therefore, if following the status stage of a control write transfer a usb host were to immediately start the next transfer, the new setup packet could override the data payload of the data stage of the previous control write. the response of the sie can be summarized as follows: 1. the sie will only respond to valid trans actions, and will ignore non-valid ones. 2. the sie will generate an interrupt when a valid transaction is completed or when the fifo is corrupted. fifo corruption occur s during an out or setup transaction to a valid internal address, that ends with a non-valid crc. 3. an incoming data packet is valid if the count is < endpoint size + 2 (includes crc) and passes all error checking; 4. an in will be ignored by an out configured endpoint and visa versa. 5. the in and out pid status is updat ed at the end of a transaction. 6. the setup pid status is updated at the beginning of the data packet phase. 7. the entire endpoint 0 mode register and the count register ar e locked to cpu writes at the end of any transaction to that endpoint in which an ack is transferred. these registers are only unlocked by a cpu read of the register, which should be done by the firmware only after the transaction is complete. th is represents about a 1- s window in which the cpu is locked from register writes to these usb regist ers. normally the firmware should perform a register read at the beginning of the endpoint isrs to unlock and get the mode register information. the interlock on the mode and count registers ensures that properties of incoming packets changes to the internal register made by the sie on receiving an incoming packet from the host interrupt 3 2 1 0 token count buffer dval dtog dval count setup in out ack 3 2 1 0 response int byte count (bits 0..5, figure 17-4) sie?s response to the host endpoint mode encoding data valid (bit 6, figure 17-4) received token (setup/in/out) data0/1 (bit7 figure 17-4) pid status bits (bit[7..5], figure 17-2) endpoint mode bits changed by the sie the validity of the received data the quality status of the dma buffer the number of received bytes acknowledge phase completed legend: tx : transmit uc : unchanged rx : receive tx0 :transmit 0 length packet available for control endpoint only x: don?t care [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 41 of 51 the firmware recognizes the changes that the sie might have made during the previous transaction . note that the setup bit of the mode register is not locked. this mean s that before writing to the mode register , firmware must first read the register to make sure that the setup bit is not set (which indicates a setu p was received, while processing the current usb request). this read will of course unlock the register. so care must be taken not to overwrite the register elsewhere. table 19-2. details of modes fo r differing traffic conditions (see table 19-1 for the decode legend) setup (if accepting setups) properties of incoming packet changes made by sie to internal registers and mode bits mode bits token count buffer dval dtog dval count setup in out ack mode bits response intr see table 19-1 setup <= 10 data valid updates 1 updates 1 uc uc 1 0 0 0 1 ack yes see table 19-1 setup > 10 junk x updates updates updates 1 uc uc uc nochange ignore yes see table 19-1 setup x junk invalid updates 0 updates 1 uc uc uc nochange ignore yes properties of incoming packet changes made by sie to internal registers and mode bits mode bits token count buffer dval dtog dval count setup in out ack mode bits response intr disabled 0 0 0 0 x x uc x uc uc uc uc uc uc uc nochange ignore no nak in/out 0 0 0 1 out x uc x uc uc uc uc uc 1 uc nochange nak yes 0 0 0 1 in x uc x uc uc uc uc 1 uc uc nochange nak yes ignore in/out 0 1 0 0 out x uc x uc uc uc uc uc uc uc nochange ignore no 0 1 0 0 in x uc x uc uc uc uc uc uc uc nochange ignore no stall in/out 0 0 1 1 out x uc x uc uc uc uc uc 1 uc nochange stall yes 0 0 1 1 in x uc x uc uc uc uc 1 uc uc nochange stall yes control write properties of incoming packet changes made by sie to internal registers and mode bits mode bits token count buffer dval dtog dval count setup in out ack mode bits response intr normal out/premature status in 1 0 1 1 out <= 10 data valid updates 1 updates uc uc 1 1 1 0 1 0 ack yes 1 0 1 1 out > 10 junk x updates updates updates uc uc 1 uc nochange ignore yes 1 0 1 1 out x junk invalid updates 0 updates uc uc 1 uc nochange ignore yes 1 0 1 1 in x uc x uc uc uc uc 1 uc 1 nochange tx 0 yes nak out/premature status in 1 0 1 0 out <= 10 uc valid uc uc uc uc uc 1 uc nochange nak yes 1 0 1 0 out > 10 uc x uc uc uc uc uc uc uc nochange ignore no 1 0 1 0 out x uc invalid uc uc uc uc uc uc uc nochange ignore no 1 0 1 0 in x uc x uc uc uc uc 1 uc 1 nochange tx 0 yes status in/extra out 0 1 1 0 out <= 10 uc valid uc uc uc uc uc 1 uc 0 0 1 1 stall yes 0 1 1 0 out > 10 uc x uc uc uc uc uc uc uc nochange ignore no 0 1 1 0 out x uc invalid uc uc uc uc uc uc uc nochange ignore no 0 1 1 0 in x uc x uc uc uc uc 1 uc 1 nochange tx 0 yes control read properties of incoming packet changes made by sie to internal registers and mode bits mode bits token count buffer dval dtog dval count setup in out ack mode bits response intr normal in/premature status out 1 1 1 1 out 2 uc valid 1 1 updates uc uc 1 1 nochange ack yes 1 1 1 1 out 2 uc valid 0 1 updates uc uc 1 uc 0 0 1 1 stall yes 1 1 1 1 out !=2 uc valid updates 1 updates uc uc 1 uc 0 0 1 1 stall yes 1 1 1 1 out > 10 uc x uc uc uc uc uc uc uc nochange ignore no 1 1 1 1 out x uc invalid uc uc uc uc uc uc uc nochange ignore no 1 1 1 1 in x uc x uc uc uc uc 1 uc 1 1 1 1 0 ack (back) yes nak in/premature status out 1 1 1 0 out 2 uc valid 1 1 updates uc uc 1 1 nochange ack yes 1 1 1 0 out 2 uc valid 0 1 updates uc uc 1 uc 0 0 1 1 stall yes [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 42 of 51 1 1 1 0 out !=2 uc valid updates 1 updates uc uc 1 uc 0 0 1 1 stall yes 1 1 1 0 out > 10 uc x uc uc uc uc uc uc uc nochange ignore no 1 1 1 0 out x uc invalid uc uc uc uc uc uc uc nochange ignore no 1 1 1 0 in x uc x uc uc uc uc 1 uc uc nochange nak yes status out/extra in 0 0 1 0 out 2 uc valid 1 1 updates uc uc 1 1 nochange ack yes 0 0 1 0 out 2 uc valid 0 1 updates uc uc 1 uc 0 0 1 1 stall yes 0 0 1 0 out !=2 uc valid updates 1 updates uc uc 1 uc 0 0 1 1 stall yes 0 0 1 0 out > 10 uc x uc uc uc uc uc uc uc nochange ignore no 0 0 1 0 out x uc invalid uc uc uc uc 1 uc uc nochange ignore no 0 0 1 0 in x uc x uc uc uc uc 1 uc uc 0 0 1 1 stall yes out endpoint properties of incoming packet changes made by sie to internal registers and mode bits mode bits token count buffer dval dtog dval count setup in out ack mode bits response intr normal out/erroneous in 1 0 0 1 out <= 10 data valid updates 1 updates uc uc uc 1 1 0 0 0 ack yes 1 0 0 1 out > 10 junk x updates updates updates uc uc uc uc nochange ignore yes 1 0 0 1 out x junk invalid updates 0 updates uc uc uc uc nochange ignore yes 1 0 0 1 in x uc x uc uc uc uc uc uc uc nochange ignore no (stall [3] = 0) 1 0 0 1 in x uc x uc uc uc uc uc uc uc nochange stall no (stall [3] = 1) nak out/erroneous in 1 0 0 0 out <= 10 uc valid uc uc uc uc uc 1 uc nochange nak yes 1 0 0 0 out > 10 uc x uc uc uc uc uc uc uc nochange ignore no 1 0 0 0 out x uc invalid uc uc uc uc uc uc uc nochange ignore no 1 0 0 0 in x uc x uc uc uc uc uc uc uc nochange ignore no isochronous endpoint (out) 0 1 0 1 out x updates updates updates updates updates uc uc 1 1 nochange rx yes 0 1 0 1 in x uc x uc uc uc uc uc uc uc nochange ignore no in endpoint properties of incoming packet changes made by sie to internal registers and mode bits mode bits token count buffer dval dtog dval count setup in out ack mode bits response intr normal in/erroneous out 1 1 0 1 out x uc x uc uc uc uc uc uc uc nochange ignore no (stall [3] = 0) 1 1 0 1 out x uc x uc uc uc uc uc uc uc nochange stall no (stall [3] = 1) 1 1 0 1 in x uc x uc uc uc uc 1 uc 1 1 1 0 0 ack (back) yes nak in/erroneous out 1 1 0 0 out x uc x uc uc uc uc uc uc uc nochange ignore no 1 1 0 0 in x uc x uc uc uc uc 1 uc uc nochange nak yes isochronous endpoint (in) 0 1 1 1 out x uc x uc uc uc uc uc uc uc nochange ignore no 0 1 1 1 in x uc x uc uc uc uc 1 uc uc nochange tx yes note: 3. stall bit is bit 7 of the usb non-control device endpoint mode registers. for more information, refer to sec. table 19-2. details of modes fo r differing traffic conditions (see table 19-1 for the decode legend) (continued) [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 43 of 51 20.0 register summary address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read/write/ both/- default/ reset gpio configuration ports 0, 1, 2 and 3 0x00 port 0 data p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 bbbbbbbb 11111111 0x01 port 1 data p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 bbbbbbbb 11111111 0x02 port 2 data p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 bbbbbbbb 11111111 0x03 port 3 data p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 bbbbbbbb 11111111 0x04 port 0 interrupt enable p0.7 intr enable p0.6 intr enable p0.5 intr enable p0.4 intr enable p0.3 intr enable p0.2 intr enable p0.1 intr enable p0.0 intr enable wwwwwwww 00000000 0x05 port 1 interrupt enable p1.7 intr enable p1.6 intr enable p1.5 intr enable p1.4 intr enable reserved p1.2 intr enable p1.1 intr enable p1.0 intr enable wwwwwwww 00000000 0x06 port 2 interrupt enable p2.7 intr enable p2.6 intr enable p2.5 intr enable p2.4 intr enable p2.3 intr enable reserved reserved reserved wwwwwwww 00000000 0x07 port 3 interrupt enable reserved reserved reserved reserved reserved reserved p3.1 intr enable p3.0 intr enable wwwwwwww 00000000 0x08 gpio configuration port 3 config bit 1 port 3 config bit 0 port 2 config bit 1 port 2 config bit 0 port 1 config bit 1 port 1 config bit 0 port 0 config bit 1 port 0 config bit 0 bbbbbbbb 00000000 hapi i 2 c 0x09 hapi/i 2 c configuration i 2 c position reserved reserved reserved reserved reserved i 2 c port width reserved bbbbbbbb 00000000 endpoint a0, ai and a2 configuration 0x10 usb device address a device address a enable device address a bit 6 device address a bit 5 device address a bit 4 device address a bit 3 device address a bit 2 device address a bit 1 device address a bit 0 bbbbbbbb 00000000 0x11 ep a0 counter register data 0/1 to g g l e data valid byte count bit 5 byte count bit 4 byte count bit 3 byte count bit 2 byte count bit 1 byte count bit 0 bbbbbbbb 00000000 0x12 ep a0 mode register endpoint0 setup received endpoint0 in received endpoint0 out received ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 bbbbbbbb 00000000 0x13 ep a1 counter register data 0/1 to g g l e data valid byte count bit 5 byte count bit 4 byte count bit 3 byte count bit 2 byte count bit 1 byte count bit 0 bbbbbbbb 00000000 0x14 ep a1 mode register stall - - ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 bbbbbbbb 00000000 0x15 ep a2 counter register data 0/1 to g g l e data valid byte count bit 5 byte count bit 4 byte count bit 3 byte count bit 2 byte count bit 1 byte count bit 0 bbbbbbbb 00000000 0x16 ep a2 mode register stall - - ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 bbbbbbbb 00000000 usb cs 0x1f usb status and control endpoint size endpoint mode d+ upstream d? upstream bus activity control bit 2 control bit 1 control bit 0 bbrrbbbb -0xx0000 interrupt 0x20 global interrupt enable reserved i 2 c interrupt enable gpio interrupt enable reserved usb hub interrupt enable 1.024-ms interrupt enable 128- s interrupt enable usb bus reset interrupt enable - bbbbbbb -0000000 0x21 endpoint interrupt enable reserved reserved reserved epb1 interrupt enable epb0 interrupt enable epa2 interrupt enable epa1 interrupt enable epa0 interrupt enable --- bbbbb ---00000 timer 0x24 timer (lsb) timer bit 7 timer bit 6 timer bit 5 timer bit 4 timer bit 3 timer bit 2 timer bit 1 timer bit 0 rrrrrrrr 00000000 0x25 timer (msb) reserved reserved reserved reserved timer bit 11 timer bit 10 time bit 9 timer bit 8 ----rrrr ----0000 0x26 wdt clear x x6 x x x 3 x2 x x wwwwwwww xxxxxxxx i 2 c 0x28 i 2 c control and status mstr mode continue/ busy xmit mode ack addr arb lost/ restart received stop i 2 c enable bbbbbbbb 00000000 0x29 i 2 c data i 2 c data 7 i 2 c data 6 i 2 c data 5 i 2 c data 4 i 2 c data 3 i 2 c data 2 i 2 c data 1 i 2 c data 0 bbbbbbbb xxxxxxxx dac port 0x30 dac data timer bit 7 timer bit 6 timer bit 5 timer bit 4 timer bit 3 timer bit 2 timer bit 1 timer bit 0 rrrrrrrr 00000000 0x31 dac interrupt enable) reserved reserved reserved reserved timer bit 11 timer bit 10 time bit 9 timer bit 8 ----rrrr ----0000 0x32 dac interrupt polarity 0x38- 0x3f das isink x x6 x x x 3 x2 x x wwwwwwww endpoint a3, a4 configuration 0x40 reserved reserved reserved reserved re served reserved reserved reserved reserved bbbbbbbb 00000000 0x41 ep a3 counter register data 0/1 to g g l e data valid byte count bit 5 byte count bit 4 byte count bit 3 byte count bit 2 byte count bit 1 byte count bit 0 bbbbbbbb 00000000 0x42 ep a3 mode register endpoint 0 setup received endpoint 0 in received endpoint 0 out received ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 bbbbbbbb 00000000 0x43 ep a4 counter register data 0/1 to g g l e data valid byte count bit 5 byte count bit 4 byte count bit 3 byte count bit 2 byte count bit 1 byte count bit 0 bbbbbbbb 00000000 0x44 ep a4 mode register stall - - ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 bbbbbbbb 00000000 [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 44 of 51 note: b: read and write w: write r: read 21.0 sample schematic reserved 0x48 reserved reserved reserved reserved reserved re served reserved reserved reserved reserved 00000000 0x49 reserved reserved reserved reserved reserved re served reserved reserved reserved reserved 00000000 0x4a reserved reserved reserved reserved reserved re served reserved reserved reserved reserved 00000000 0x4b reserved reserved reserved reserved reserved re served reserved reserved reserved reserved 00000000 0x4c reserved reserved reserved reserved reserved re served reserved reserved reserved reserved --000000 0x4d reserved reserved reserved reserved reserved re served reserved reserved reserved reserved 00000000 0x4e reserved reserved reserved reserved reserved re served reserved reserved reserved reserved 00000000 0x4f reserved reserved reserved reserved reserved re served reserved reserved reserved reserved 00000000 0x50 reserved reserved reserved reserved reserved re served reserved reserved reserved reserved 00000000 0x51 reserved reserved reserved reserved reserved re served reserved reserved reserved reserved 00000000 0x52 reserved reserved reserved reserved reserv ed reserved reserved reserved reserved reserved 00000000 0xff process status & control irq pending watchdog reset usb bus reset interrupt power-on reset suspend interrupt enable sense reserved run rbbbbrbb 00010001 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read/write/ both/- default/ reset xtalo xtali d0? d0+ v cc vref vpp gnd gnd in gnd out usb-b vbus d? d+ gnd .01 f 6.000 mhz 22x2(r ext ) 0v 0v 0v vbus vref 0v .01 f 0v 2.2 f 2.2 f shell 10m 4.7 nf 250vac optional 3.3v regulator (r uup ) vref 1.5k [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 45 of 51 22.0 absolute maximum ratings storage temperature ........................................................................................................... ............. .............. ....?65c to +150c ambient temperature with power applied ......................................................................................... ........................0c to +70c supply voltage on v cc relative to v ss .................................................................................................................... ?0.5v to +7 .0v dc input voltage............................................................................................................... ............................ ?0.5v to +v cc +0.5v dc voltage applied to outputs in high z state.................................................................................. ........... ?0.5v to +v cc +0.5v power dissipation ...................... ........................................................................................ ............................................... 500 mw static discharge voltage ...................................................................................................... ............................................. >2000v latch-up current .............................................................................................................. .............................................. >200 ma max output sink current into port 0, 1, 2, 3, and da c[1:0] pins ............................................................... ....................... 60 ma max output sink current into dac[7:2] pins ......... ............................................................................ ................................. 10 ma 23.0 electrical characteristics f osc = 6 mhz; operating temperature = 0 to 70c, v cc = 4.0v to 5.25v parameter description conditions min. max. unit general v ref reference voltage 3.3v 5% 3.15 3.45 v v pp programming voltage (disabled) ?0.4 0.4 v i cc v cc operating current no gpio source current 50 ma i sb1 supply current?suspend mode 50 a i ref v ref operating current note 5 30 ma i il input leakage current any pin 1 a usb interface v di differential input sensitivity | (d+)?(d?) | 0.2 v v cm differential input common mode range 0.8 2.5 v v se single ended receiver threshold 0.8 2.0 v c in transceiver capacitance 20 pf i lo hi-z state data line leakage 0 v < v in < 3.3 v ?10 10 a r ext external usb series resistor in series with each usb pin 19 21 ? r uup external upstream usb pull-up resistor 1.5 k ? 5%, d+ to v reg 1.425 1.575 k ? power on reset t vccs v cc ramp rate linear ramp 0v to v cc [4] 0100ms usb upstream v uoh static output high 15 k ? 5% to gnd 2.8 3.6 v v uol static output low 1.5 k ? 5% to v ref 0.3 v z o usb driver output impedance including r ext resistor 28 44 ? general purpose i/o (gpio) r up pull-up resistance (typical 14 k ?) 8.0 24.0 k ? v ith input threshold voltage all ports, low to high edge 20% 40% v cc v h input hysteresis voltage all ports, high to low edge 2% 8% v cc v ol port 0,1,2,3 output low voltage i ol = 3 ma i ol = 8 ma 0.4 2.0 v v v oh output high voltage i oh = 1.9 ma (all ports 0,1,2,3) 2.4 v notes: 4. power-on reset occurs whenever the voltage on v cc is below approximately 2.5v. 5. this is based on transitions every 2 full-speed bit times on average. [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 46 of 51 dac interface r up dac pull-up resistance (typical 14 k ?) 8.0 24.0 k ? i sink0(0) dac[7:2] sink current (0) v out = 2.0v dc 0.1 0.3 ma i sink0(f) dac[7:2] sink current (f) v out = 2.0v dc 0.5 1.5 ma i sink1(0) dac[1:0] sink current (0) v out = 2.0v dc 1.6 4.8 ma i sink1(f) dac[1:0] sink current (f) v out = 2.0v dc 8 24 ma i range programmed isink ratio: max/min v out = 2.0v dc [6] 46 t ratio tracking ratio dac[1:0] to dac[7:2] v out = 2.0v [7] 14 22 i sinkdac dac sink current v out = 2.0v dc 1.6 4.8 ma i lin differential nonlinearity dac port [8] 0.6 lsb 24.0 switching characteristics (f osc = 6.0 mhz) parameter descrip tion min. max. unit clock source f osc clock rate 6 0.25% mhz t cyc clock period 166.25 167.08 ns t ch clock high time 0.45 t cyc ns t cl clock low time 0.45 t cyc ns usb full speed signaling [9] t rfs transition rise time 4 20 ns t ffs transition fall time 4 20 ns t rfmfs rise / fall time matching; (t r /t f ) 90 111 % t dratefs full speed date rate 12 0.25% mb/s dac interface t sink current sink response time 0.8 s hapi read cycle timing t rd read pulse width 15 ns t oed oe low to data valid [10, 11] 40 ns t oez oe high to data high-z [11] 20 ns t oedr oe low to data_ready deasserted [10, 11] 060ns hapi write cycle timing t wr write strobe width 15 ns t dstb data valid to stb high (data set-up time) [11] 5ns t stbz stb high to data high-z (data hold time) [11] 15 ns t stble stb low to latch_empty deasserted [10, 11] 050ns timer signals t watch watchdog timer period 8.192 14.336 ms notes: 6. irange: i sinkn (15)/ i sinkn (0) for the same pin. 7. t ratio = i sink1 [1:0](n)/i sink0 [7:2](n) for the same n, programmed. 8. i lin measured as largest step size vs. nominal according to measured full scale and zero programmed values. 9. per table 7-6 of revision 1.1 of usb specification. 10. for 25-pf load. 11. assumes chip select cs is asserted (low). 23.0 electrical characteristics (continued) f osc = 6 mhz; operating temperature = 0 to 70c, v cc = 4.0v to 5.25v parameter description conditions min. max. unit [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 47 of 51 figure 24-1. clock timing figure 24-2. usb data signal timing figure 24-3. hapi read by external interface from usb microcontroller clock t cyc t cl t ch 90% 10% 90% 10% d ? d + t r t r oe (p2.5, input) data (output) stb (p2.4, input) dreadypin (p2.3, output) internal write internal addr port0 d[23:0] t oed t oez t rd t oedr cs (p2.6, input) int (shown for drdy polarity=0) interrupt generated (ready) [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 48 of 51 25.0 ordering information ordering code prom size package type operating range cy7c64013c-sxc 8 kb 28-pin (300-mil) soic commercial CY7C64013C-PXC 8 kb 28-pin (300-mil) pdip commercial cy7c64013c-sxct 8 kb 28-pin (300-mil) soic - tape reel commercial cy7c64113c-pvxc 8 kb 48-pin (300-mil) ssop commercial data (input) lemptypin (p2.2, output) internal read internal addr port0 d[23:0] t stble t wr t stbz t dstb oe (p2.5, input) cs (p2.6, input) stb (p2.4, input) (not empty) (shown for lempty polarity=0) int interrupt generated figure 24-4. hapi write by extern al device to usb microcontroller [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 49 of 51 26.0 package diagrams 48-lead shrunk small outline package 51-85061-*c dimensions in inches [mm] min. max. seating plane 0.260[6.60] 0.295[7.49] 0.090[2.28] 0.110[2.79] 0.055[1.39] 0.065[1.65] 0.015[0.38] 0.020[0.50] 0.015[0.38] 0.060[1.52] 0.120[3.05] 0.140[3.55] 0.009[0.23] 0.012[0.30] 0.310[7.87] 0.385[9.78] 0.290[7.36] 0.325[8.25] 0.030[0.76] 0.080[2.03] 0.115[2.92] 0.160[4.06] 0.140[3.55] 0.190[4.82] 1.345[34.16] 1.385[35.18] 3 min. 1 14 15 28 reference jedec mo-095 lead end option see lead end option see lead end option (lead #1, 14, 15 & 28) package weight: 2.15 gms 28-lead (300-mil) pdip 51-85014-*d [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 50 of 51 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all product and company names mentio ned in this document are the tradema rks of their respective holders. 26.0 package diagrams (continued) pin1id 0.291[7.39] 0.300[7.62] 0.394[10.01] 0.419[10.64] 0.050[1.27] typ. 0.092[2.33] 0.105[2.67] 0.004[0.10] 0.0118[0.30] seating plane 0.0091[0.23] 0.0125[3.17] 0.015[0.38] 0.050[1.27] 0.013[0.33] 0.019[0.48] 0.026[0.66] 0.032[0.81] 0.697[17.70] 0.713[18.11] 0.004[0.10] 1 14 15 28 * * * part # s28.3 standard pkg. sz28.3 lead free pkg. min. max. note : 1. jedec std ref mo-119 2. body length dimension does not include mold protrusion/end flash,but mold protrusion/end flash shall not exceed 0.010 in (0.254 mm) per side 3. dimensions in inches 4. package weight 0.85gms does include mold mismatch and are measured at the mold parting line. 51-85026-*d 28-lead (300-mil) molded soic [+] feedback
cy7c64013c cy7c64113c document #: 38-08001 rev. *b page 51 of 51 document history page document title: cy7c64013c, cy7c64113c full-speed usb (12 mbps) function document number: 38-08001 rev. ecn no. issue date orig. of change description of change ** 109962 12/16/01 szv change from spec number: 38-00626 to 38-08001 *a 129715 02/05/04 mon added register bit definitions added default bit state of each register corrected the schematic (location of the pull up on d+) added register summary modified tables 19-1 and 19-2 provided more explanation regarding locking/unlocking mechanism of the mode register. *b 429099 see ecn tyj changed part numbers to t he ?c? types. included ?cypress perform? logo. updated part numbers in the ordering section. [+] feedback

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